ar9344.dtsi 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "ar934x.dtsi"
  3. / {
  4. compatible = "qca,ar9344";
  5. };
  6. &cpuintc {
  7. qca,ddr-wb-channel-interrupts = <3>, <4>, <5>;
  8. qca,ddr-wb-channels = <&ddr_ctrl 2>, <&ddr_ctrl 0>,
  9. <&ddr_ctrl 1>;
  10. };
  11. &rst {
  12. intc2: interrupt-controller {
  13. compatible = "qca,ar9340-intc";
  14. interrupt-parent = <&cpuintc>;
  15. interrupts = <2>;
  16. interrupt-controller;
  17. #interrupt-cells = <1>;
  18. qca,int-status-addr = <0xac>;
  19. qca,pending-bits = <0xf>, /* wmac */
  20. <0x1f0>; /* pcie rc1 */
  21. qca,ddr-wb-channel-interrupts = <0>, <1>;
  22. qca,ddr-wb-channels = <&ddr_ctrl 4>, <&ddr_ctrl 3>;
  23. };
  24. };
  25. &apb {
  26. pcie: pcie-controller@180c0000 {
  27. compatible = "qcom,ar9340-pci", "qcom,ar7240-pci";
  28. #address-cells = <3>;
  29. #size-cells = <2>;
  30. bus-range = <0x0 0x0>;
  31. reg = <0x180c0000 0x1000>, /* CRP */
  32. <0x180f0000 0x100>, /* CTRL */
  33. <0x14000000 0x1000>; /* CFG */
  34. reg-names = "crp_base", "ctrl_base", "cfg_base";
  35. ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
  36. 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
  37. interrupt-parent = <&intc2>;
  38. interrupts = <1>;
  39. interrupt-controller;
  40. #interrupt-cells = <1>;
  41. interrupt-map-mask = <0 0 0 1>;
  42. interrupt-map = <0 0 0 0 &pcie 0>;
  43. status = "disabled";
  44. };
  45. };
  46. &wmac {
  47. interrupt-parent = <&intc2>;
  48. interrupts = <0>;
  49. };