1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162 |
- // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- #include "ar934x.dtsi"
- / {
- compatible = "qca,ar9344";
- };
- &cpuintc {
- qca,ddr-wb-channel-interrupts = <3>, <4>, <5>;
- qca,ddr-wb-channels = <&ddr_ctrl 2>, <&ddr_ctrl 0>,
- <&ddr_ctrl 1>;
- };
- &rst {
- intc2: interrupt-controller {
- compatible = "qca,ar9340-intc";
- interrupt-parent = <&cpuintc>;
- interrupts = <2>;
- interrupt-controller;
- #interrupt-cells = <1>;
- qca,int-status-addr = <0xac>;
- qca,pending-bits = <0xf>, /* wmac */
- <0x1f0>; /* pcie rc1 */
- qca,ddr-wb-channel-interrupts = <0>, <1>;
- qca,ddr-wb-channels = <&ddr_ctrl 4>, <&ddr_ctrl 3>;
- };
- };
- &apb {
- pcie: pcie-controller@180c0000 {
- compatible = "qcom,ar9340-pci", "qcom,ar7240-pci";
- #address-cells = <3>;
- #size-cells = <2>;
- bus-range = <0x0 0x0>;
- reg = <0x180c0000 0x1000>, /* CRP */
- <0x180f0000 0x100>, /* CTRL */
- <0x14000000 0x1000>; /* CFG */
- reg-names = "crp_base", "ctrl_base", "cfg_base";
- ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
- 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
- interrupt-parent = <&intc2>;
- interrupts = <1>;
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 1>;
- interrupt-map = <0 0 0 0 &pcie 0>;
- status = "disabled";
- };
- };
- &wmac {
- interrupt-parent = <&intc2>;
- interrupts = <0>;
- };
|