0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch 1.9 KB

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  1. From 4a4f869ec58ed8910b9b2e68d0eee50957e9bb20 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <john@phrozen.org>
  3. Date: Mon, 25 Jun 2018 15:52:10 +0200
  4. Subject: [PATCH 17/33] dt-bindings: PCI: qcom,ar7100: adds binding doc
  5. With the driver being converted from platform_data to pure OF, we need to
  6. also add some docs.
  7. Cc: Rob Herring <robh+dt@kernel.org>
  8. Cc: devicetree@vger.kernel.org
  9. Signed-off-by: John Crispin <john@phrozen.org>
  10. ---
  11. .../devicetree/bindings/pci/qcom,ar7100-pci.txt | 38 ++++++++++++++++++++++
  12. 1 file changed, 38 insertions(+)
  13. create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
  14. --- /dev/null
  15. +++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
  16. @@ -0,0 +1,38 @@
  17. +* Qualcomm Atheros AR7100 PCI express root complex
  18. +
  19. +Required properties:
  20. +- compatible: should contain "qcom,ar7100-pci" to identify the core.
  21. +- reg: Should contain the register ranges as listed in the reg-names property.
  22. +- reg-names: Definition: Must include the following entries
  23. + - "cfg_base" IO Memory
  24. +- #address-cells: set to <3>
  25. +- #size-cells: set to <2>
  26. +- ranges: ranges for the PCI memory and I/O regions
  27. +- interrupt-map-mask and interrupt-map: standard PCI
  28. + properties to define the mapping of the PCIe interface to interrupt
  29. + numbers.
  30. +- #interrupt-cells: set to <1>
  31. +- interrupt-controller: define to enable the builtin IRQ cascade.
  32. +
  33. +Optional properties:
  34. +- interrupt-parent: phandle to the MIPS IRQ controller
  35. +
  36. +* Example for ar7100
  37. + pcie-controller@180c0000 {
  38. + compatible = "qca,ar7100-pci";
  39. + #address-cells = <3>;
  40. + #size-cells = <2>;
  41. + bus-range = <0x0 0x0>;
  42. + reg = <0x17010000 0x100>;
  43. + reg-names = "cfg_base";
  44. + ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000
  45. + 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
  46. + interrupt-parent = <&cpuintc>;
  47. + interrupts = <2>;
  48. +
  49. + interrupt-controller;
  50. + #interrupt-cells = <1>;
  51. +
  52. + interrupt-map-mask = <0 0 0 1>;
  53. + interrupt-map = <0 0 0 0 &pcie0 0>;
  54. + };