1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192 |
- --- /dev/null
- +++ b/arch/mips/ath79/gpio.c
- @@ -0,0 +1,59 @@
- +/*
- + * Atheros AR71XX/AR724X/AR913X GPIO API support
- + *
- + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
- + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- + *
- + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
- + *
- + * This program is free software; you can redistribute it and/or modify it
- + * under the terms of the GNU General Public License version 2 as published
- + * by the Free Software Foundation.
- + */
- +#include <linux/kernel.h>
- +#include <linux/module.h>
- +#include <linux/io.h>
- +#include <linux/gpio.h>
- +#include <asm/mach-ath79/ar71xx_regs.h>
- +#include <asm/mach-ath79/ath79.h>
- +#include "common.h"
- +
- +void __iomem *ath79_gpio_base;
- +EXPORT_SYMBOL_GPL(ath79_gpio_base);
- +
- +static void __iomem *ath79_gpio_get_function_reg(void)
- +{
- + u32 reg = 0;
- +
- + if (soc_is_ar71xx() ||
- + soc_is_ar724x() ||
- + soc_is_ar913x() ||
- + soc_is_ar933x())
- + reg = AR71XX_GPIO_REG_FUNC;
- + else if (soc_is_ar934x())
- + reg = AR934X_GPIO_REG_FUNC;
- + else
- + BUG();
- +
- + return ath79_gpio_base + reg;
- +}
- +
- +void ath79_gpio_function_setup(u32 set, u32 clear)
- +{
- + void __iomem *reg = ath79_gpio_get_function_reg();
- +
- + __raw_writel((__raw_readl(reg) & ~clear) | set, reg);
- + /* flush write */
- + __raw_readl(reg);
- +}
- +
- +void ath79_gpio_function_enable(u32 mask)
- +{
- + ath79_gpio_function_setup(mask, 0);
- +}
- +
- +void ath79_gpio_function_disable(u32 mask)
- +{
- + ath79_gpio_function_setup(0, mask);
- +}
- --- a/arch/mips/include/asm/mach-ath79/ath79.h
- +++ b/arch/mips/include/asm/mach-ath79/ath79.h
- @@ -118,6 +118,7 @@ static inline int soc_is_qca955x(void)
- void ath79_ddr_wb_flush(unsigned int reg);
- void ath79_ddr_set_pci_windows(void);
-
- +extern void __iomem *ath79_gpio_base;
- extern void __iomem *ath79_pll_base;
- extern void __iomem *ath79_reset_base;
-
- --- a/arch/mips/ath79/dev-common.c
- +++ b/arch/mips/ath79/dev-common.c
- @@ -156,4 +156,5 @@ void __init ath79_gpio_init(void)
- }
-
- platform_device_register(&ath79_gpio_device);
- + ath79_gpio_base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
- }
- --- a/arch/mips/ath79/common.h
- +++ b/arch/mips/ath79/common.h
- @@ -24,6 +24,9 @@ unsigned long ath79_get_sys_clk_rate(con
-
- void ath79_ddr_ctrl_init(void);
-
- +void ath79_gpio_function_enable(u32 mask);
- +void ath79_gpio_function_disable(u32 mask);
- +void ath79_gpio_function_setup(u32 set, u32 clear);
- void ath79_gpio_init(void);
-
- #endif /* __ATH79_COMMON_H */
|