ar9342_iodata_etg3-r.dts 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include "ar9344.dtsi"
  6. / {
  7. compatible = "iodata,etg3-r", "qca,ar9344";
  8. model = "I-O DATA ETG3-R";
  9. aliases {
  10. led-boot = &power;
  11. led-failsafe = &power;
  12. led-running = &power;
  13. led-upgrade = &power;
  14. };
  15. leds {
  16. compatible = "gpio-leds";
  17. power: power {
  18. label = "etg3-r:green:power";
  19. gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
  20. default-state = "on";
  21. };
  22. notification {
  23. label = "etg3-r:green:notification";
  24. gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
  25. };
  26. };
  27. keys {
  28. compatible = "gpio-keys-polled";
  29. poll-interval = <20>;
  30. reset {
  31. label = "reset";
  32. linux,code = <KEY_RESTART>;
  33. gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
  34. debounce-interval = <60>;
  35. };
  36. };
  37. };
  38. &ref {
  39. clock-frequency = <40000000>;
  40. };
  41. &spi {
  42. num-cs = <1>;
  43. status = "okay";
  44. flash@0 {
  45. compatible = "jedec,spi-nor";
  46. reg = <0>;
  47. spi-max-frequency = <25000000>;
  48. partitions {
  49. compatible = "fixed-partitions";
  50. #address-cells = <1>;
  51. #size-cells = <1>;
  52. partition@0 {
  53. label = "u-boot";
  54. reg = <0x000000 0x040000>;
  55. read-only;
  56. };
  57. partition@40000 {
  58. label = "u-boot-env";
  59. reg = <0x040000 0x010000>;
  60. };
  61. partition@50000 {
  62. compatible = "denx,uimage";
  63. label = "firmware";
  64. reg = <0x050000 0x780000>;
  65. };
  66. partition@7d0000 {
  67. label = "Config";
  68. reg = <0x07d0000 0x10000>;
  69. read-only;
  70. };
  71. partition@7e0000 {
  72. label = "Rsv";
  73. reg = <0x07e0000 0x10000>;
  74. read-only;
  75. };
  76. partition@7f0000 {
  77. label = "ART";
  78. reg = <0x7f0000 0x010000>;
  79. read-only;
  80. };
  81. };
  82. };
  83. };
  84. &mdio0 {
  85. status = "okay";
  86. phy0: ethernet-phy@0 {
  87. reg = <0>;
  88. phy-mode = "rgmii";
  89. qca,ar8327-initvals = <
  90. 0x04 0x07600000 /* PORT0 PAD MODE CTRL */
  91. 0x50 0xffb7ffb7 /* LED_CTRL0 */
  92. 0x54 0xffb7ffb7 /* LED_CTRL1 */
  93. 0x58 0xffb7ffb7 /* LED_CTRL2 */
  94. 0x5c 0x03ffff00 /* LED_CTRL3 */
  95. 0x7c 0x0000007e /* PORT0_STATUS */
  96. >;
  97. };
  98. };
  99. &eth0 {
  100. status = "okay";
  101. pll-data = <0x0e000000 0x00000101 0x00001616>;
  102. phy-mode = "rgmii";
  103. phy-handle = <&phy0>;
  104. gmac-config {
  105. device = <&gmac>;
  106. rgmii-gmac0 = <1>;
  107. rxd-delay = <3>;
  108. rxdv-delay = <3>;
  109. };
  110. };
  111. &uart {
  112. status = "okay";
  113. };