ar9344_dlink_dir-8x5.dtsi 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include "ar9344.dtsi"
  6. / {
  7. chosen {
  8. bootargs = "console=ttyS0,115200";
  9. };
  10. keys {
  11. compatible = "gpio-keys";
  12. reset {
  13. linux,code = <KEY_RESTART>;
  14. gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
  15. debounce-interval = <60>;
  16. };
  17. wps {
  18. linux,code = <KEY_WPS_BUTTON>;
  19. gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
  20. debounce-interval = <60>;
  21. };
  22. };
  23. };
  24. &eth0 {
  25. status = "okay";
  26. /* default for ar934x, except for 1000M */
  27. pll-data = <0x06000000 0x00000101 0x00001616>;
  28. phy-mode = "rgmii";
  29. phy-handle = <&phy0>;
  30. };
  31. &mdio0 {
  32. status = "okay";
  33. phy-mask = <0>;
  34. phy0: ethernet-phy@0 {
  35. reg = <0>;
  36. qca,ar8327-initvals = <
  37. /* GPL code drop (bsp.h & athrs17_phy.c) */
  38. 0x10 0xc1000000 /* PWS_REG_VALUE */
  39. 0x04 0x07600000 /* PORT0 PAD Mode */
  40. 0x0c 0x01000000 /* PORT6 PAD Mode */
  41. 0x7c 0x0000007e /* PORT0_STATUS */
  42. 0x94 0x0000007e /* PORT6_STATUS */
  43. >;
  44. };
  45. };
  46. &pcie {
  47. status = "okay";
  48. ath9k: wifi@0,0 {
  49. compatible = "pci168c,0030";
  50. reg = <0x0000 0 0 0 0>;
  51. qca,no-eeprom;
  52. gpio-controller;
  53. #gpio-cells = <2>;
  54. };
  55. };
  56. &ref {
  57. clock-frequency = <40000000>;
  58. };
  59. &spi {
  60. status = "okay";
  61. num-cs = <1>;
  62. flash@0 {
  63. compatible = "jedec,spi-nor";
  64. reg = <0>;
  65. spi-max-frequency = <25000000>;
  66. partitions {
  67. compatible = "fixed-partitions";
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. partition@0 {
  71. label = "uboot";
  72. reg = <0x000000 0x010000>;
  73. read-only;
  74. };
  75. partition@10000 {
  76. label = "nvram";
  77. reg = <0x010000 0x010000>;
  78. read-only;
  79. };
  80. partition@20000 {
  81. label = "firmware";
  82. reg = <0x020000 0xF90000>;
  83. compatible = "denx,uimage";
  84. };
  85. partition@fb0000 {
  86. label = "lang";
  87. reg = <0xfb0000 0x030000>;
  88. read-only;
  89. };
  90. partition@fe0000 {
  91. label = "mac";
  92. reg = <0xfe0000 0x010000>;
  93. read-only;
  94. };
  95. partition@ff0000 {
  96. label = "art";
  97. reg = <0xff0000 0x010000>;
  98. read-only;
  99. };
  100. };
  101. };
  102. };
  103. &uart {
  104. status = "okay";
  105. };
  106. &usb {
  107. status = "okay";
  108. #address-cells = <1>;
  109. #size-cells = <0>;
  110. hub_port1: port@1 {
  111. reg = <1>;
  112. #trigger-source-cells = <0>;
  113. };
  114. };
  115. &usb_phy {
  116. status = "okay";
  117. };
  118. &wmac {
  119. status = "okay";
  120. qca,no-eeprom;
  121. };