ar934x.dtsi 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include <dt-bindings/clock/ath79-clk.h>
  3. #include "ath79.dtsi"
  4. / {
  5. compatible = "qca,ar9340";
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. chosen {
  9. bootargs = "console=ttyS0,115200";
  10. };
  11. cpus {
  12. #address-cells = <1>;
  13. #size-cells = <0>;
  14. cpu@0 {
  15. device_type = "cpu";
  16. compatible = "mips,mips74Kc";
  17. clocks = <&pll ATH79_CLK_CPU>;
  18. reg = <0>;
  19. };
  20. };
  21. clocks {
  22. #address-cells = <1>;
  23. #size-cells = <1>;
  24. ranges;
  25. ref: ref {
  26. #clock-cells = <0>;
  27. compatible = "fixed-clock";
  28. clock-output-names = "ref";
  29. };
  30. };
  31. ahb {
  32. compatible = "simple-bus";
  33. ranges;
  34. #address-cells = <1>;
  35. #size-cells = <1>;
  36. apb: apb {
  37. compatible = "simple-bus";
  38. ranges;
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. ddr_ctrl: memory-controller@18000000 {
  42. compatible = "qca,ar9340-ddr-controller",
  43. "qca,ar7240-ddr-controller";
  44. reg = <0x18000000 0x12c>;
  45. #qca,ddr-wb-channel-cells = <1>;
  46. };
  47. uart: uart@18020000 {
  48. compatible = "ns16550a";
  49. reg = <0x18020000 0x2c>;
  50. interrupts = <3>;
  51. clocks = <&pll ATH79_CLK_REF>;
  52. clock-names = "uart";
  53. reg-io-width = <4>;
  54. reg-shift = <2>;
  55. no-loopback-test;
  56. status = "disabled";
  57. };
  58. gpio: gpio@18040000 {
  59. compatible = "qca,ar9340-gpio";
  60. reg = <0x18040000 0x2c>;
  61. interrupts = <2>;
  62. ngpios = <23>;
  63. gpio-controller;
  64. #gpio-cells = <2>;
  65. interrupt-controller;
  66. #interrupt-cells = <2>;
  67. };
  68. pinmux: pinmux@1804002c {
  69. compatible = "pinctrl-single";
  70. reg = <0x1804002c 0x44>;
  71. #size-cells = <0>;
  72. pinctrl-single,bit-per-mux;
  73. pinctrl-single,register-width = <32>;
  74. pinctrl-single,function-mask = <0x1>;
  75. #pinctrl-cells = <2>;
  76. jtag_disable_pins: pinmux_jtag_disable_pins {
  77. pinctrl-single,bits = <0x40 0x2 0x2>;
  78. };
  79. };
  80. pll: pll-controller@18050000 {
  81. compatible = "qca,ar9340-pll", "syscon";
  82. reg = <0x18050000 0x4c>;
  83. #clock-cells = <1>;
  84. clocks = <&ref>;
  85. clock-names = "ref";
  86. clock-output-names = "cpu", "ddr", "ahb";
  87. };
  88. wdt: wdt@18060008 {
  89. compatible = "qca,ar9340-wdt", "qca,ar7130-wdt";
  90. reg = <0x18060008 0x8>;
  91. interrupts = <4>;
  92. clocks = <&pll ATH79_CLK_AHB>;
  93. clock-names = "wdt";
  94. };
  95. rst: reset-controller@1806001c {
  96. compatible = "qca,ar9340-reset", "qca,ar7100-reset";
  97. reg = <0x1806001c 0x4>;
  98. #reset-cells = <1>;
  99. };
  100. gmac: gmac@18070000 {
  101. compatible = "qca,ar9340-gmac";
  102. reg = <0x18070000 0x14>;
  103. };
  104. wmac: wmac@18100000 {
  105. compatible = "qca,ar9340-wmac";
  106. reg = <0x18100000 0x20000>;
  107. status = "disabled";
  108. };
  109. };
  110. usb: usb@1b000000 {
  111. compatible = "generic-ehci";
  112. reg = <0x1b000000 0x1d8>;
  113. interrupts = <3>;
  114. resets = <&rst 5>;
  115. reset-names = "usb-host";
  116. has-transaction-translator;
  117. caps-offset = <0x100>;
  118. phy-names = "usb-phy";
  119. phys = <&usb_phy>;
  120. status = "disabled";
  121. };
  122. spi: spi@1f000000 {
  123. compatible = "qca,ar9340-spi", "qca,ar7100-spi";
  124. reg = <0x1f000000 0x1c>;
  125. clocks = <&pll ATH79_CLK_AHB>;
  126. clock-names = "ahb";
  127. #address-cells = <1>;
  128. #size-cells = <0>;
  129. status = "disabled";
  130. };
  131. };
  132. usb_phy: usb-phy {
  133. compatible = "qca,ar9340-usb-phy", "qca,ar7200-usb-phy";
  134. reset-names = "usb-phy", "usb-suspend-override";
  135. resets = <&rst 4>, <&rst 3>;
  136. #phy-cells = <0>;
  137. status = "disabled";
  138. };
  139. };
  140. &mdio0 {
  141. compatible = "qca,ar9340-mdio";
  142. resets = <&rst 22>;
  143. reset-names = "mdio";
  144. };
  145. &eth0 {
  146. compatible = "qca,ar9340-eth", "syscon", "simple-mfd";
  147. pll-data = <0x16000000 0x00000101 0x00001616>;
  148. pll-reg = <0x4 0x2c 17>;
  149. pll-handle = <&pll>;
  150. resets = <&rst 9>;
  151. reset-names = "mac";
  152. };
  153. &mdio1 {
  154. status = "okay";
  155. compatible = "qca,ar9340-mdio";
  156. resets = <&rst 23>;
  157. reset-names = "mdio";
  158. builtin-switch;
  159. builtin_switch: switch0@1f {
  160. compatible = "qca,ar8229-builtin";
  161. reg = <0x1f>;
  162. resets = <&rst 8>;
  163. reset-names = "switch";
  164. phy-mode = "gmii";
  165. phy4-mii-enable;
  166. mdio-bus {
  167. #address-cells = <1>;
  168. #size-cells = <0>;
  169. swphy0: ethernet-phy@0 {
  170. reg = <0>;
  171. phy-mode = "mii";
  172. };
  173. swphy4: ethernet-phy@4 {
  174. reg = <4>;
  175. phy-mode = "mii";
  176. };
  177. };
  178. };
  179. };
  180. &eth1 {
  181. compatible = "qca,ar9340-eth", "syscon", "simple-mfd";
  182. resets = <&rst 13>;
  183. reset-names = "mac";
  184. phy-mode = "gmii";
  185. fixed-link {
  186. speed = <1000>;
  187. full-duplex;
  188. };
  189. };