qca953x.dtsi 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include <dt-bindings/clock/ath79-clk.h>
  3. #include "ath79.dtsi"
  4. / {
  5. compatible = "qca,qca9530";
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. chosen {
  9. bootargs = "console=ttyS0,115200n8";
  10. };
  11. cpus {
  12. #address-cells = <1>;
  13. #size-cells = <0>;
  14. cpu@0 {
  15. device_type = "cpu";
  16. compatible = "mips,mips24Kc";
  17. clocks = <&pll ATH79_CLK_CPU>;
  18. reg = <0>;
  19. };
  20. };
  21. extosc: ref {
  22. compatible = "fixed-clock";
  23. #clock-cells = <0>;
  24. clock-output-names = "ref";
  25. clock-frequency = <25000000>;
  26. };
  27. ahb {
  28. apb {
  29. ddr_ctrl: memory-controller@18000000 {
  30. compatible = "qca,ar9530-ddr-controller",
  31. "qca,ar7240-ddr-controller";
  32. reg = <0x18000000 0x128>;
  33. #qca,ddr-wb-channel-cells = <1>;
  34. };
  35. uart: uart@18020000 {
  36. compatible = "ns16550a";
  37. reg = <0x18020000 0x20>;
  38. interrupts = <3>;
  39. clocks = <&pll ATH79_CLK_REF>;
  40. clock-names = "uart";
  41. reg-io-width = <4>;
  42. reg-shift = <2>;
  43. no-loopback-test;
  44. status = "disabled";
  45. };
  46. usb_phy: usb-phy@18030000 {
  47. compatible = "qca,ar7200-usb-phy";
  48. reg = <0x18030000 0x100>;
  49. #phy-cells = <0>;
  50. reset-names = "usb-phy", "usb-suspend-override";
  51. resets = <&rst 4>, <&rst 3>;
  52. status = "disabled";
  53. };
  54. gpio: gpio@18040000 {
  55. compatible = "qca,ar9530-gpio",
  56. "qca,ar9340-gpio";
  57. reg = <0x18040000 0x28>;
  58. interrupts = <2>;
  59. ngpios = <20>;
  60. gpio-controller;
  61. #gpio-cells = <2>;
  62. interrupt-controller;
  63. #interrupt-cells = <2>;
  64. };
  65. pinmux: pinmux@1804002c {
  66. compatible = "pinctrl-single";
  67. reg = <0x1804002c 0x48>;
  68. #size-cells = <0>;
  69. pinctrl-single,bit-per-mux;
  70. pinctrl-single,register-width = <32>;
  71. pinctrl-single,function-mask = <0x1>;
  72. #pinctrl-cells = <2>;
  73. jtag_disable_pins: pinmux_jtag_disable_pins {
  74. pinctrl-single,bits = <0x40 0x2 0x2>;
  75. };
  76. };
  77. pll: pll-controller@18050000 {
  78. compatible = "qca,qca9530-pll", "syscon";
  79. reg = <0x18050000 0x48>;
  80. #clock-cells = <1>;
  81. clock-output-names = "cpu", "ddr", "ahb";
  82. clocks = <&extosc>;
  83. };
  84. wdt: wdt@18060008 {
  85. compatible = "qca,qca9530-wdt", "qca,ar7130-wdt";
  86. reg = <0x18060008 0x8>;
  87. interrupts = <4>;
  88. clocks = <&pll ATH79_CLK_AHB>;
  89. clock-names = "wdt";
  90. };
  91. rst: reset-controller@1806001c {
  92. compatible = "qca,qca9530-reset",
  93. "qca,ar7100-reset";
  94. reg = <0x1806001c 0xac>;
  95. #reset-cells = <1>;
  96. intc2: interrupt-controller {
  97. compatible = "qca,ar9340-intc";
  98. interrupt-parent = <&cpuintc>;
  99. interrupts = <2>;
  100. interrupt-controller;
  101. #interrupt-cells = <1>;
  102. qca,int-status-addr = <0xac>;
  103. qca,pending-bits = <0xf>, /* wmac */
  104. <0x1f0>; /* pcie rc1 */
  105. qca,ddr-wb-channel-interrupts = <0>, <1>;
  106. qca,ddr-wb-channels = <&ddr_ctrl 4>, <&ddr_ctrl 3>;
  107. };
  108. };
  109. pcie0: pcie-controller@180c0000 {
  110. compatible = "qcom,ar7240-pci";
  111. #address-cells = <3>;
  112. #size-cells = <2>;
  113. bus-range = <0x0 0x0>;
  114. reg = <0x180c0000 0x1000>, /* CRP */
  115. <0x180f0000 0x100>, /* CTRL */
  116. <0x14000000 0x1000>; /* CFG */
  117. reg-names = "crp_base", "ctrl_base", "cfg_base";
  118. ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
  119. 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
  120. interrupt-parent = <&intc2>;
  121. interrupts = <1>;
  122. interrupt-controller;
  123. #interrupt-cells = <1>;
  124. interrupt-map-mask = <0 0 0 1>;
  125. interrupt-map = <0 0 0 0 &pcie0 0>;
  126. status = "disabled";
  127. };
  128. gmac: gmac@18070000 {
  129. compatible = "qca,ar9330-gmac";
  130. reg = <0x18070000 0x4>;
  131. };
  132. wmac: wmac@18100000 {
  133. compatible = "qca,qca9530-wmac";
  134. reg = <0x18100000 0x230000>;
  135. interrupt-parent = <&intc2>;
  136. interrupts = <0>;
  137. status = "disabled";
  138. };
  139. };
  140. usb0: usb@1b000000 {
  141. compatible = "generic-ehci";
  142. reg = <0x1b000000 0x1000>;
  143. interrupts = <3>;
  144. resets = <&rst 5>;
  145. reset-names = "usb-host";
  146. dr_mode = "host";
  147. has-transaction-translator;
  148. caps-offset = <0x100>;
  149. phy-names = "usb-phy";
  150. phys = <&usb_phy>;
  151. status = "disabled";
  152. };
  153. spi: spi@1f000000 {
  154. compatible = "qca,ar9530-spi", "qca,ar7100-spi";
  155. reg = <0x1f000000 0x10>;
  156. clocks = <&pll ATH79_CLK_AHB>;
  157. clock-names = "ahb";
  158. status = "disabled";
  159. #address-cells = <1>;
  160. #size-cells = <0>;
  161. };
  162. };
  163. };
  164. &cpuintc {
  165. qca,ddr-wb-channel-interrupts = <3>, <4>, <5>;
  166. qca,ddr-wb-channels = <&ddr_ctrl 2>, <&ddr_ctrl 0>,
  167. <&ddr_ctrl 1>;
  168. };
  169. &eth0 {
  170. compatible = "qca,qca9530-eth", "syscon";
  171. pll-data = <0x82000101 0x80000101 0x80001313>;
  172. reg = <0x19000000 0x200
  173. 0x18070000 0x4>;
  174. pll-reg = <0x4 0x2c 17>;
  175. pll-handle = <&pll>;
  176. reset-names = "mac";
  177. resets = <&rst 9>;
  178. phy-mode = "mii";
  179. };
  180. &mdio1 {
  181. status = "okay";
  182. resets = <&rst 23>;
  183. reset-names = "mdio";
  184. builtin-switch;
  185. builtin_switch: switch0@1f {
  186. compatible = "qca,ar8229-builtin";
  187. reg = <0x1f>;
  188. resets = <&rst 8>;
  189. reset-names = "switch";
  190. phy-mode = "gmii";
  191. phy4-mii-enable;
  192. mdio-bus {
  193. #address-cells = <1>;
  194. #size-cells = <0>;
  195. swphy0: ethernet-phy@0 {
  196. reg = <0>;
  197. phy-mode = "mii";
  198. };
  199. swphy4: ethernet-phy@4 {
  200. reg = <4>;
  201. phy-mode = "mii";
  202. };
  203. };
  204. };
  205. };
  206. &eth1 {
  207. status = "okay";
  208. compatible = "qca,qca9530-eth", "syscon", "simple-mfd";
  209. resets = <&rst 13>;
  210. reset-names = "mac";
  211. phy-mode = "gmii";
  212. fixed-link {
  213. speed = <1000>;
  214. full-duplex;
  215. };
  216. };