qca9558_openmesh_om5p-ac-v2.dts 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. #include "qca9557.dtsi"
  6. / {
  7. compatible = "openmesh,om5p-ac-v2", "qca,qca9557";
  8. model = "OpenMesh OM5P-AC V2";
  9. extosc: ref {
  10. compatible = "fixed-clock";
  11. #clock-cells = <0>;
  12. clock-output-names = "ref";
  13. clock-frequency = <40000000>;
  14. };
  15. leds {
  16. compatible = "gpio-leds";
  17. power {
  18. label = "om5pac:blue:power";
  19. gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
  20. };
  21. wifi_green {
  22. label = "om5pac:green:wifi";
  23. gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
  24. };
  25. wifi_yellow {
  26. label = "om5pac:yellow:wifi";
  27. gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
  28. };
  29. wifi_red {
  30. label = "om5pac:red:wifi";
  31. gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
  32. };
  33. };
  34. keys {
  35. compatible = "gpio-keys-polled";
  36. poll-interval = <100>;
  37. button0 {
  38. label = "reset";
  39. linux,code = <KEY_RESTART>;
  40. gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
  41. };
  42. };
  43. gpio-export {
  44. compatible = "gpio-export";
  45. #size-cells = <0>;
  46. gpio_pa_dcdc {
  47. gpio-export,name = "om5pac:pa_dcdc";
  48. gpio-export,output = <1>;
  49. gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
  50. };
  51. gpio_pa_high {
  52. gpio-export,name = "om5pac:pa_high";
  53. gpio-export,output = <1>;
  54. gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
  55. };
  56. };
  57. };
  58. &pinmux {
  59. pinmux_pa_dcdc_pins {
  60. pinctrl-single,bits = <0x0 0xff00 0x0>;
  61. };
  62. pinmux_pa_high_pins {
  63. pinctrl-single,bits = <0x10 0xff 0x0>;
  64. };
  65. };
  66. &pcie0 {
  67. status = "okay";
  68. };
  69. &uart {
  70. status = "okay";
  71. };
  72. &pll {
  73. clocks = <&extosc>;
  74. };
  75. &spi {
  76. status = "okay";
  77. num-cs = <1>;
  78. flash@0 {
  79. compatible = "jedec,spi-nor";
  80. reg = <0>;
  81. spi-max-frequency = <25000000>;
  82. partitions {
  83. compatible = "fixed-partitions";
  84. #address-cells = <1>;
  85. #size-cells = <1>;
  86. partition@0 {
  87. label = "u-boot";
  88. reg = <0x000000 0x040000>;
  89. read-only;
  90. };
  91. partition@1 {
  92. label = "u-boot-env";
  93. reg = <0x040000 0x010000>;
  94. };
  95. partition@2 {
  96. compatible = "denx,uimage";
  97. label = "firmware";
  98. reg = <0x850000 0x7a0000>;
  99. };
  100. partition@3 {
  101. label = "ART";
  102. reg = <0xff0000 0x010000>;
  103. read-only;
  104. };
  105. };
  106. };
  107. };
  108. &mdio0 {
  109. status = "okay";
  110. phy4: ethernet-phy@4 {
  111. reg = <4>;
  112. phy-mode = "rgmii-id";
  113. };
  114. };
  115. &mdio1 {
  116. status = "okay";
  117. phy1: ethernet-phy@1 {
  118. reg = <1>;
  119. phy-mode = "sgmii";
  120. };
  121. };
  122. &eth0 {
  123. status = "okay";
  124. pll-data = <0x82000101 0x80000101 0x80001313>;
  125. phy-handle = <&phy4>;
  126. phy-mode = "rgmii";
  127. };
  128. &eth1 {
  129. status = "okay";
  130. pll-data = <0x03000101 0x80000101 0x80001313>;
  131. phy-handle = <&phy1>;
  132. phy-mode = "sgmii";
  133. };