076-v4.11-0004-net-phy-bcm7xxx-Implement-EGPHY-workaround-for-7278.patch 2.1 KB

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  1. From: Florian Fainelli <f.fainelli@gmail.com>
  2. Date: Fri, 20 Jan 2017 12:36:34 -0800
  3. Subject: [PATCH] net: phy: bcm7xxx: Implement EGPHY workaround for 7278
  4. Implement the HW design team recommended workaround in for 7278. Since
  5. the GPHY now returns its revision information in MII_PHYS_ID[23] we need
  6. to check whether the revision provided in flags is 0 or not.
  7. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  8. Signed-off-by: David S. Miller <davem@davemloft.net>
  9. ---
  10. --- a/drivers/net/phy/bcm7xxx.c
  11. +++ b/drivers/net/phy/bcm7xxx.c
  12. @@ -163,12 +163,43 @@ static int bcm7xxx_28nm_e0_plus_afe_conf
  13. return 0;
  14. }
  15. +static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
  16. +{
  17. + /* +1 RC_CAL codes for RL centering for both LT and HT conditions */
  18. + bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
  19. +
  20. + /* Cut master bias current by 2% to compensate for RC_CAL offset */
  21. + bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
  22. +
  23. + /* Improve hybrid leakage */
  24. + bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
  25. +
  26. + /* Change rx_on_tune 8 to 0xf */
  27. + bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
  28. +
  29. + /* Change 100Tx EEE bandwidth */
  30. + bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
  31. +
  32. + /* Enable ffe zero detection for Vitesse interoperability */
  33. + bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
  34. +
  35. + r_rc_cal_reset(phydev);
  36. +
  37. + return 0;
  38. +}
  39. +
  40. static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
  41. {
  42. u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
  43. u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
  44. int ret = 0;
  45. + /* Newer devices have moved the revision information back into a
  46. + * standard location in MII_PHYS_ID[23]
  47. + */
  48. + if (rev == 0)
  49. + rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
  50. +
  51. pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
  52. phydev_name(phydev), phydev->drv->name, rev, patch);
  53. @@ -192,6 +223,9 @@ static int bcm7xxx_28nm_config_init(stru
  54. case 0x10:
  55. ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
  56. break;
  57. + case 0x01:
  58. + ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
  59. + break;
  60. default:
  61. break;
  62. }