BR-6478AC-V2.dts 3.5 KB

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  1. /*
  2. * Device Tree file for the Edimax BR-6478AC V2
  3. * based on Linksys E1700
  4. *
  5. * Copyright (C) 2016 Rohan Murch <rohan.murch@gmail.com>
  6. * Copyright (C) 2016 Hans Ulli Kroll <ulli.kroll@googlemail.com>
  7. * Copyright (C) 2017 James McKenzie <openwrt@madingley.org>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. /dts-v1/;
  14. #include "mt7620a.dtsi"
  15. #include <dt-bindings/gpio/gpio.h>
  16. #include <dt-bindings/input/input.h>
  17. / {
  18. compatible = "edimax,br-6478ac-v2", "ralink,mt7620a-soc";
  19. model = "Edimax BR-6478AC v2";
  20. aliases {
  21. led-boot = &led_power;
  22. led-failsafe = &led_power;
  23. led-running = &led_power;
  24. led-upgrade = &led_power;
  25. };
  26. chosen {
  27. bootargs = "console=ttyS0,57600";
  28. };
  29. gpio-keys-polled {
  30. compatible = "gpio-keys-polled";
  31. poll-interval = <20>;
  32. reset_wps {
  33. label = "reset_wps";
  34. gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  35. linux,code = <KEY_RESTART>;
  36. };
  37. };
  38. gpio-leds {
  39. compatible = "gpio-leds";
  40. led_power: power {
  41. label = "br-6478ac-v2:white:power";
  42. gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
  43. };
  44. internet {
  45. label = "br-6478ac-v2:blue:internet";
  46. gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
  47. };
  48. wlan {
  49. label = "br-6478ac-v2:blue:wlan";
  50. gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
  51. };
  52. usb {
  53. label = "br-6478ac-v2:blue:usb";
  54. gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
  55. trigger-sources = <&ohci_port1>, <&ehci_port1>;
  56. linux,default-trigger = "usbport";
  57. };
  58. };
  59. gpio_export {
  60. compatible = "gpio-export";
  61. #size-cells = <0>;
  62. usb-power {
  63. gpio-export,name="usb-power";
  64. gpio-export,output=<1>;
  65. gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
  66. };
  67. };
  68. };
  69. &gpio2 {
  70. status = "okay";
  71. };
  72. &spi0 {
  73. status = "okay";
  74. flash@0 {
  75. compatible = "jedec,spi-nor";
  76. reg = <0 0>;
  77. spi-max-frequency = <10000000>;
  78. partitions {
  79. compatible = "fixed-partitions";
  80. #address-cells = <1>;
  81. #size-cells = <1>;
  82. partition@0 {
  83. label = "u-boot";
  84. reg = <0x0 0x30000>;
  85. read-only;
  86. };
  87. partition@30000 {
  88. label = "u-boot-env";
  89. reg = <0x30000 0x10000>;
  90. read-only;
  91. };
  92. factory: partition@40000 {
  93. label = "factory";
  94. reg = <0x40000 0x10000>;
  95. read-only;
  96. };
  97. partition@50000 {
  98. label = "cimage";
  99. reg = <0x50000 0x20000>;
  100. read-only;
  101. };
  102. partition@70000 {
  103. label = "firmware";
  104. reg = <0x00070000 0x00790000>;
  105. };
  106. };
  107. };
  108. };
  109. &pinctrl {
  110. state_default: pinctrl0 {
  111. gpio {
  112. ralink,group = "i2c", "uartf", "nd_sd";
  113. ralink,function = "gpio";
  114. };
  115. };
  116. };
  117. &ethernet {
  118. status = "okay";
  119. mtd-mac-address = <&factory 0x4>;
  120. pinctrl-names = "default";
  121. pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
  122. mediatek,portmap = "wllll";
  123. port@5 {
  124. status = "okay";
  125. mediatek,fixed-link = <1000 1 1 1>;
  126. phy-mode = "rgmii";
  127. };
  128. mdio-bus {
  129. status = "okay";
  130. phy0: ethernet-phy@0 {
  131. reg = <0>;
  132. phy-mode = "rgmii";
  133. };
  134. phy1: ethernet-phy@1 {
  135. reg = <1>;
  136. phy-mode = "rgmii";
  137. };
  138. phy2: ethernet-phy@2 {
  139. reg = <2>;
  140. phy-mode = "rgmii";
  141. };
  142. phy3: ethernet-phy@3 {
  143. reg = <3>;
  144. phy-mode = "rgmii";
  145. };
  146. phy4: ethernet-phy@4 {
  147. reg = <4>;
  148. phy-mode = "rgmii";
  149. };
  150. phy1f: ethernet-phy@1f {
  151. reg = <0x1f>;
  152. phy-mode = "rgmii";
  153. };
  154. };
  155. };
  156. &gsw {
  157. mediatek,port4 = "gmac";
  158. };
  159. &wmac {
  160. ralink,mtd-eeprom = <&factory 0>;
  161. };
  162. &pcie {
  163. status = "okay";
  164. };
  165. &pcie0 {
  166. wifi@0,0 {
  167. reg = <0x0000 0 0 0 0>;
  168. mediatek,mtd-eeprom = <&factory 0x8000>;
  169. mediatek,2ghz = <0>;
  170. };
  171. };
  172. &ehci {
  173. status = "okay";
  174. };
  175. &ohci {
  176. status = "okay";
  177. };