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K2G.dts 2.2 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "phicomm,k2g", "ralink,mt7620a-soc";
  7. model = "Phicomm K2G";
  8. aliases {
  9. led-boot = &led_blue;
  10. led-failsafe = &led_blue;
  11. led-running = &led_blue;
  12. led-upgrade = &led_blue;
  13. serial0 = &uartlite;
  14. };
  15. gpio-leds {
  16. compatible = "gpio-leds";
  17. led_blue: blue {
  18. label = "k2g:blue:status";
  19. gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
  20. };
  21. yellow {
  22. label = "k2g:yellow:status";
  23. gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
  24. };
  25. red {
  26. label = "k2g:red:status";
  27. gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
  28. };
  29. };
  30. gpio-keys-polled {
  31. compatible = "gpio-keys-polled";
  32. poll-interval = <20>;
  33. reset {
  34. label = "reset";
  35. gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
  36. linux,code = <KEY_RESTART>;
  37. };
  38. };
  39. };
  40. &spi0 {
  41. status = "okay";
  42. m25p80@0 {
  43. compatible = "jedec,spi-nor";
  44. reg = <0>;
  45. spi-max-frequency = <24000000>;
  46. partitions {
  47. compatible = "fixed-partitions";
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. partition@0 {
  51. reg = <0x0 0x30000>;
  52. label = "u-boot";
  53. read-only;
  54. };
  55. partition@30000 {
  56. reg = <0x30000 0x10000>;
  57. label = "u-boot-env";
  58. read-only;
  59. };
  60. factory: partition@40000 {
  61. reg = <0x40000 0x10000>;
  62. label = "factory";
  63. read-only;
  64. };
  65. partition@50000 {
  66. reg = <0x50000 0x50000>;
  67. label = "permanent_config";
  68. read-only;
  69. };
  70. partition@a0000 {
  71. reg = <0xa0000 0x760000>;
  72. label = "firmware";
  73. };
  74. };
  75. };
  76. };
  77. &pinctrl {
  78. state_default: pinctrl0 {
  79. gpio {
  80. ralink,group = "i2c", "uartf";
  81. ralink,function = "gpio";
  82. };
  83. };
  84. };
  85. &ethernet {
  86. pinctrl-names = "default";
  87. pinctrl-0 = <&rgmii2_pins &mdio_pins>;
  88. mtd-mac-address = <&factory 0x28>;
  89. mediatek,portmap = "llllw";
  90. port@5 {
  91. status = "okay";
  92. phy-handle = <&phy5>;
  93. phy-mode = "rgmii";
  94. };
  95. mdio-bus {
  96. status = "okay";
  97. phy5: ethernet-phy@5 {
  98. reg = <5>;
  99. phy-mode = "rgmii";
  100. };
  101. };
  102. };
  103. &pcie {
  104. status = "okay";
  105. };
  106. &pcie0 {
  107. mt76@0,0 {
  108. reg = <0x0000 0 0 0 0>;
  109. mediatek,mtd-eeprom = <&factory 0x8000>;
  110. ieee80211-freq-limit = <5000000 6000000>;
  111. };
  112. };
  113. &wmac {
  114. ralink,mtd-eeprom = <&factory 0>;
  115. pinctrl-names = "default";
  116. pinctrl-0 = <&pa_pins>;
  117. };