MZK-750DHP.dts 2.1 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "planex,mzk-750dhp", "ralink,mt7620a-soc";
  7. model = "Planex MZK-750DHP";
  8. aliases {
  9. led-boot = &led_power;
  10. led-failsafe = &led_power;
  11. led-running = &led_power;
  12. led-upgrade = &led_power;
  13. };
  14. gpio-leds {
  15. compatible = "gpio-leds";
  16. wps {
  17. label = "mzk-750dhp:green:wps";
  18. gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
  19. };
  20. led_power: power {
  21. label = "mzk-750dhp:green:power";
  22. gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  23. };
  24. wlan5g {
  25. label = "mzk-750dhp:green:wlan5g";
  26. gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
  27. };
  28. };
  29. gpio-keys-polled {
  30. compatible = "gpio-keys-polled";
  31. poll-interval = <20>;
  32. s1 {
  33. label = "reset";
  34. gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
  35. linux,code = <KEY_RESTART>;
  36. };
  37. s2 {
  38. label = "wps";
  39. gpios = <&gpio2 19 GPIO_ACTIVE_LOW>;
  40. linux,code = <KEY_WPS_BUTTON>;
  41. };
  42. };
  43. };
  44. &gpio1 {
  45. status = "okay";
  46. };
  47. &gpio2 {
  48. status = "okay";
  49. };
  50. &spi0 {
  51. status = "okay";
  52. m25p80@0 {
  53. compatible = "jedec,spi-nor";
  54. reg = <0>;
  55. spi-max-frequency = <10000000>;
  56. partitions {
  57. compatible = "fixed-partitions";
  58. #address-cells = <1>;
  59. #size-cells = <1>;
  60. partition@0 {
  61. label = "u-boot";
  62. reg = <0x0 0x30000>;
  63. read-only;
  64. };
  65. partition@30000 {
  66. label = "u-boot-env";
  67. reg = <0x30000 0x10000>;
  68. read-only;
  69. };
  70. factory: partition@40000 {
  71. label = "factory";
  72. reg = <0x40000 0x10000>;
  73. read-only;
  74. };
  75. partition@50000 {
  76. label = "firmware";
  77. reg = <0x50000 0x7b0000>;
  78. };
  79. };
  80. };
  81. };
  82. &pinctrl {
  83. state_default: pinctrl0 {
  84. gpio {
  85. ralink,group = "i2c", "spi refclk", "rgmii1", "nd_sd";
  86. ralink,function = "gpio";
  87. };
  88. };
  89. };
  90. &ethernet {
  91. pinctrl-names = "default";
  92. pinctrl-0 = <&ephy_pins>;
  93. mtd-mac-address = <&factory 0x4>;
  94. mediatek,portmap = "llllw";
  95. };
  96. &gsw {
  97. mediatek,port4 = "ephy";
  98. };
  99. &wmac {
  100. ralink,mtd-eeprom = <&factory 0>;
  101. };
  102. &pcie {
  103. status = "okay";
  104. };
  105. &pcie0 {
  106. mt76@0,0 {
  107. reg = <0x0000 0 0 0 0>;
  108. mediatek,mtd-eeprom = <&factory 0x8000>;
  109. };
  110. };