MZK-WDPR.dts 1.4 KB

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  1. /dts-v1/;
  2. #include "rt3050.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. / {
  5. compatible = "planex,mzk-wdpr", "ralink,rt3052-soc";
  6. model = "Planex MZK-WDPR";
  7. chosen {
  8. bootargs = "console=ttyS0,115200";
  9. };
  10. cfi@1f000000 {
  11. compatible = "cfi-flash";
  12. reg = <0x1f000000 0x800000>;
  13. bank-width = <2>;
  14. device-width = <2>;
  15. partitions {
  16. compatible = "fixed-partitions";
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. partition@0 {
  20. label = "u-boot";
  21. reg = <0x0 0x30000>;
  22. read-only;
  23. };
  24. partition@30000 {
  25. label = "u-boot-env";
  26. reg = <0x30000 0x10000>;
  27. read-only;
  28. };
  29. factory: partition@40000 {
  30. label = "factory";
  31. reg = <0x40000 0x10000>;
  32. read-only;
  33. };
  34. partition@7f0000 {
  35. label = "Data3G";
  36. reg = <0x7f0000 0x10000>;
  37. read-only;
  38. };
  39. partition@50000 {
  40. label = "firmware";
  41. reg = <0x50000 0x680000>;
  42. };
  43. };
  44. };
  45. gpio-export {
  46. compatible = "gpio-export";
  47. lcd_ctrl1 {
  48. gpio-export,name = "lcd_ctrl1";
  49. gpio-export,output = <0>;
  50. gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
  51. };
  52. };
  53. };
  54. &pinctrl {
  55. state_default: pinctrl0 {
  56. gpio {
  57. ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf";
  58. ralink,function = "gpio";
  59. };
  60. };
  61. };
  62. &ethernet {
  63. mtd-mac-address = <&factory 0x28>;
  64. };
  65. &esw {
  66. mediatek,portmap = <0x2f>;
  67. };
  68. &wmac {
  69. ralink,mtd-eeprom = <&factory 0>;
  70. };
  71. &otg {
  72. status = "okay";
  73. };