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NA930.dts 2.8 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "sercomm,na930", "ralink,mt7620a-soc";
  7. model = "Sercomm NA930";
  8. aliases {
  9. led-boot = &led_power;
  10. led-failsafe = &led_power;
  11. led-running = &led_power;
  12. led-upgrade = &led_power;
  13. };
  14. chosen {
  15. bootargs = "console=ttyS1,57600";
  16. };
  17. nand {
  18. compatible = "mtk,mt7620-nand";
  19. partitions {
  20. compatible = "fixed-partitions";
  21. #address-cells = <1>;
  22. #size-cells = <1>;
  23. partition@0 {
  24. label = "u-boot";
  25. reg = <0x0 0x20000>;
  26. read-only;
  27. };
  28. partition@200000 {
  29. label = "factory";
  30. reg = <0x200000 0x40000>;
  31. read-only;
  32. };
  33. partition@240000 {
  34. label = "Config";
  35. reg = <0x240000 0x400000>;
  36. read-only;
  37. };
  38. partition@640000 {
  39. label = "firmware";
  40. reg = <0x640000 0x1400000>;
  41. };
  42. };
  43. };
  44. gpio-keys-polled {
  45. compatible = "gpio-keys-polled";
  46. poll-interval = <20>;
  47. reset {
  48. label = "reset";
  49. gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
  50. linux,code = <KEY_RESTART>;
  51. };
  52. zwave {
  53. label = "zwave";
  54. gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
  55. linux,code = <BTN_0>;
  56. };
  57. wps {
  58. label = "wps";
  59. gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
  60. linux,code = <KEY_WPS_BUTTON>;
  61. };
  62. };
  63. gpio-leds {
  64. compatible = "gpio-leds";
  65. zwave {
  66. label = "na930:blue:zwave";
  67. gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
  68. };
  69. status {
  70. label = "na930:blue:status";
  71. gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
  72. trigger-sources = <&ohci_port1>, <&ehci_port1>;
  73. linux,default-trigger = "usbport";
  74. };
  75. service {
  76. label = "na930:blue:service";
  77. gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
  78. };
  79. led_power: power {
  80. label = "na930:blue:power";
  81. gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
  82. };
  83. };
  84. gpio_export {
  85. compatible = "gpio-export";
  86. #size-cells = <0>;
  87. telit {
  88. gpio-export,name = "telit";
  89. gpio-export,output = <1>;
  90. gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
  91. };
  92. };
  93. };
  94. &pinctrl {
  95. state_default: pinctrl0 {
  96. gpio {
  97. ralink,group = "i2c", "rgmii2", "spi", "ephy";
  98. ralink,function = "gpio";
  99. };
  100. uartf_gpio {
  101. ralink,group = "uartf";
  102. ralink,function = "gpio uartf";
  103. };
  104. };
  105. };
  106. &uart {
  107. status = "okay";
  108. };
  109. &gpio1 {
  110. status = "okay";
  111. };
  112. &gpio2 {
  113. status = "okay";
  114. };
  115. &ethernet {
  116. status = "okay";
  117. pinctrl-names = "default";
  118. pinctrl-0 = <&rgmii1_pins &mdio_pins>;
  119. mediatek,portmap = "llllw";
  120. port@4 {
  121. status = "okay";
  122. phy-handle = <&phy4>;
  123. phy-mode = "rgmii";
  124. };
  125. port@5 {
  126. status = "okay";
  127. phy-handle = <&phy5>;
  128. phy-mode = "rgmii";
  129. };
  130. mdio-bus {
  131. status = "okay";
  132. phy4: ethernet-phy@4 {
  133. reg = <4>;
  134. phy-mode = "rgmii";
  135. };
  136. phy5: ethernet-phy@5 {
  137. reg = <5>;
  138. phy-mode = "rgmii";
  139. };
  140. };
  141. };
  142. &gsw {
  143. mediatek,port4 = "gmac";
  144. };
  145. &ehci {
  146. status = "okay";
  147. };
  148. &ohci {
  149. status = "okay";
  150. };