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PSG1218.dtsi 1.2 KB

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  1. #include "mt7620a.dtsi"
  2. #include <dt-bindings/gpio/gpio.h>
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. compatible = "phicomm,psg1218", "ralink,mt7620a-soc";
  6. gpio-keys-polled {
  7. compatible = "gpio-keys-polled";
  8. poll-interval = <20>;
  9. reset {
  10. label = "reset";
  11. gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
  12. linux,code = <KEY_RESTART>;
  13. };
  14. };
  15. };
  16. &gpio0 {
  17. status = "okay";
  18. };
  19. &spi0 {
  20. status = "okay";
  21. m25p80@0 {
  22. compatible = "jedec,spi-nor";
  23. reg = <0>;
  24. spi-max-frequency = <10000000>;
  25. partitions {
  26. compatible = "fixed-partitions";
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. partition@0 {
  30. label = "u-boot";
  31. reg = <0x0 0x30000>;
  32. read-only;
  33. };
  34. partition@20000 {
  35. label = "u-boot-env";
  36. reg = <0x30000 0x10000>;
  37. read-only;
  38. };
  39. factory: partition@30000 {
  40. label = "factory";
  41. reg = <0x40000 0x10000>;
  42. read-only;
  43. };
  44. partition@40000 {
  45. label = "firmware";
  46. reg = <0x50000 0x7b0000>;
  47. };
  48. };
  49. };
  50. };
  51. &pcie {
  52. status = "okay";
  53. };
  54. &pcie0 {
  55. mt76@0,0 {
  56. reg = <0x0000 0 0 0 0>;
  57. mediatek,mtd-eeprom = <&factory 0x8000>;
  58. ieee80211-freq-limit = <5000000 6000000>;
  59. };
  60. };
  61. &wmac {
  62. ralink,mtd-eeprom = <&factory 0>;
  63. };