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SK-WB8.dts 2.1 KB

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  1. /dts-v1/;
  2. #include "mt7621.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. / {
  6. compatible = "samknows,whitebox-v8", "mediatek,mt7621-soc";
  7. model = "SamKnows Whitebox 8";
  8. aliases {
  9. led-boot = &led_wps;
  10. led-failsafe = &led_wps;
  11. led-running = &led_wps;
  12. led-upgrade = &led_wps;
  13. };
  14. memory@0 {
  15. device_type = "memory";
  16. reg = <0x0 0x8000000>;
  17. };
  18. chosen {
  19. bootargs = "console=ttyS0,57600";
  20. };
  21. gpio-leds {
  22. compatible = "gpio-leds";
  23. led_wps: wps {
  24. label = "sk-wb8:green:wps";
  25. gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
  26. };
  27. usb {
  28. label = "sk-wb8:green:usb";
  29. gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  30. trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
  31. linux,default-trigger = "usbport";
  32. };
  33. };
  34. gpio-keys-polled {
  35. compatible = "gpio-keys-polled";
  36. poll-interval = <20>;
  37. wps {
  38. label = "wps";
  39. gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
  40. linux,code = <KEY_WPS_BUTTON>;
  41. };
  42. reset {
  43. label = "reset";
  44. gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
  45. linux,code = <KEY_RESTART>;
  46. };
  47. };
  48. };
  49. &spi0 {
  50. status = "okay";
  51. m25p80@0 {
  52. compatible = "jedec,spi-nor";
  53. reg = <0>;
  54. spi-max-frequency = <10000000>;
  55. m25p,chunked-io = <32>;
  56. partitions {
  57. compatible = "fixed-partitions";
  58. #address-cells = <1>;
  59. #size-cells = <1>;
  60. partition@0 {
  61. label = "u-boot";
  62. reg = <0x0 0x30000>;
  63. read-only;
  64. };
  65. partition@30000 {
  66. label = "u-boot-env";
  67. reg = <0x30000 0x10000>;
  68. };
  69. factory: partition@40000 {
  70. label = "factory";
  71. reg = <0x40000 0x10000>;
  72. read-only;
  73. };
  74. partition@50000 {
  75. label = "firmware";
  76. reg = <0x50000 0xfb0000>;
  77. };
  78. };
  79. };
  80. };
  81. &pcie {
  82. status = "okay";
  83. };
  84. &pcie0 {
  85. mt76@0,0 {
  86. reg = <0x0000 0 0 0 0>;
  87. mediatek,mtd-eeprom = <&factory 0x8000>;
  88. ieee80211-freq-limit = <5000000 6000000>;
  89. };
  90. };
  91. &pcie1 {
  92. mt76@0,0 {
  93. reg = <0x0000 0 0 0 0>;
  94. mediatek,mtd-eeprom = <&factory 0x0000>;
  95. };
  96. };
  97. &ethernet {
  98. mtd-mac-address = <&factory 0xe000>;
  99. };
  100. &pinctrl {
  101. state_default: pinctrl0 {
  102. gpio {
  103. ralink,group = "i2c", "uart2", "uart3", "rgmii2", "sdhci";
  104. ralink,function = "gpio";
  105. };
  106. };
  107. };