ZBT-CPE102.dts 1.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128
  1. /dts-v1/;
  2. #include "mt7620n.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "zbtlink,zbt-cpe102", "ralink,mt7620n-soc";
  7. model = "Zbtlink ZBT-CPE102";
  8. chosen {
  9. bootargs = "console=ttyS0,115200";
  10. };
  11. aliases {
  12. led-boot = &led_4g_0;
  13. led-failsafe = &led_4g_0;
  14. };
  15. gpio-leds {
  16. compatible = "gpio-leds";
  17. led_4g_0: 4g-0 {
  18. label = "zbt-cpe102:green:4g-0";
  19. gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
  20. };
  21. 4g-1 {
  22. label = "zbt-cpe102:green:4g-1";
  23. gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  24. };
  25. 4g-2 {
  26. label = "zbt-cpe102:green:4g-2";
  27. gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  28. };
  29. };
  30. gpio-keys-polled {
  31. compatible = "gpio-keys-polled";
  32. poll-interval = <20>;
  33. reset {
  34. label = "reset";
  35. gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
  36. linux,code = <KEY_RESTART>;
  37. };
  38. };
  39. };
  40. &gpio1 {
  41. status = "okay";
  42. };
  43. &gpio2 {
  44. status = "okay";
  45. };
  46. &gpio3 {
  47. status = "okay";
  48. };
  49. &spi0 {
  50. status = "okay";
  51. en25q64@0 {
  52. compatible = "jedec,spi-nor";
  53. reg = <0>;
  54. spi-max-frequency = <10000000>;
  55. partitions {
  56. compatible = "fixed-partitions";
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. partition@0 {
  60. label = "u-boot";
  61. reg = <0x0 0x30000>;
  62. read-only;
  63. };
  64. partition@30000 {
  65. label = "u-boot-env";
  66. reg = <0x30000 0x10000>;
  67. read-only;
  68. };
  69. factory: partition@40000 {
  70. label = "factory";
  71. reg = <0x40000 0x10000>;
  72. read-only;
  73. };
  74. partition@50000 {
  75. label = "firmware";
  76. reg = <0x50000 0x760000>;
  77. };
  78. };
  79. };
  80. };
  81. &ehci {
  82. status = "okay";
  83. };
  84. &ohci {
  85. status = "okay";
  86. };
  87. &ethernet {
  88. mtd-mac-address = <&factory 0x4>;
  89. mediatek,portmap = "wllll";
  90. };
  91. &wmac {
  92. ralink,mtd-eeprom = <&factory 0>;
  93. };
  94. &pinctrl {
  95. state_default: pinctrl0 {
  96. default {
  97. ralink,group = "i2c", "spi refclk", "wled";
  98. ralink,function = "gpio";
  99. };
  100. };
  101. };