ZBT-WG2626.dts 2.0 KB

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  1. /dts-v1/;
  2. #include "mt7621.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "zbtlink,zbt-wg2626", "mediatek,mt7621-soc";
  7. model = "ZBT-WG2626";
  8. aliases {
  9. led-boot = &led_status;
  10. led-failsafe = &led_status;
  11. led-running = &led_status;
  12. led-upgrade = &led_status;
  13. };
  14. memory@0 {
  15. device_type = "memory";
  16. reg = <0x0 0x1c000000>, <0x20000000 0x4000000>;
  17. };
  18. chosen {
  19. bootargs = "console=ttyS0,115200";
  20. };
  21. palmbus: palmbus@1E000000 {
  22. i2c@900 {
  23. status = "okay";
  24. };
  25. };
  26. gpio-keys-polled {
  27. compatible = "gpio-keys-polled";
  28. poll-interval = <20>;
  29. reset {
  30. label = "reset";
  31. gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
  32. linux,code = <KEY_RESTART>;
  33. };
  34. };
  35. gpio-leds {
  36. compatible = "gpio-leds";
  37. led_status: status {
  38. label = "zbt-wg2626:green:status";
  39. gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
  40. };
  41. };
  42. };
  43. &sdhci {
  44. status = "okay";
  45. };
  46. &spi0 {
  47. status = "okay";
  48. m25p80@0 {
  49. compatible = "jedec,spi-nor";
  50. reg = <0>;
  51. spi-max-frequency = <10000000>;
  52. m25p,chunked-io = <32>;
  53. partitions {
  54. compatible = "fixed-partitions";
  55. #address-cells = <1>;
  56. #size-cells = <1>;
  57. partition@0 {
  58. label = "u-boot";
  59. reg = <0x0 0x30000>;
  60. read-only;
  61. };
  62. partition@30000 {
  63. label = "u-boot-env";
  64. reg = <0x30000 0x10000>;
  65. read-only;
  66. };
  67. factory: partition@40000 {
  68. label = "factory";
  69. reg = <0x40000 0x10000>;
  70. read-only;
  71. };
  72. partition@50000 {
  73. label = "firmware";
  74. reg = <0x50000 0xfb0000>;
  75. };
  76. };
  77. };
  78. };
  79. &pcie {
  80. status = "okay";
  81. };
  82. &pcie0 {
  83. mt76@0,0 {
  84. reg = <0x0000 0 0 0 0>;
  85. mediatek,mtd-eeprom = <&factory 0x8000>;
  86. ieee80211-freq-limit = <5000000 6000000>;
  87. };
  88. };
  89. &pcie1 {
  90. mt76@0,0 {
  91. reg = <0x0000 0 0 0 0>;
  92. mediatek,mtd-eeprom = <&factory 0x0000>;
  93. ieee80211-freq-limit = <2400000 2500000>;
  94. };
  95. };
  96. &ethernet {
  97. mtd-mac-address = <&factory 0xe000>;
  98. };
  99. &pinctrl {
  100. state_default: pinctrl0 {
  101. gpio {
  102. ralink,group = "wdt", "rgmii2", "jtag", "mdio";
  103. ralink,function = "gpio";
  104. };
  105. };
  106. };