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ZBT-WG3526.dtsi 2.0 KB

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  1. #include "mt7621.dtsi"
  2. #include <dt-bindings/gpio/gpio.h>
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. compatible = "zbtlink,zbt-wg3526", "mediatek,mt7621-soc";
  6. aliases {
  7. led-boot = &led_status;
  8. led-failsafe = &led_status;
  9. led-running = &led_status;
  10. led-upgrade = &led_status;
  11. };
  12. memory@0 {
  13. device_type = "memory";
  14. reg = <0x0 0x1c000000>, <0x20000000 0x4000000>;
  15. };
  16. chosen {
  17. bootargs = "console=ttyS0,115200";
  18. };
  19. palmbus: palmbus@1E000000 {
  20. i2c@900 {
  21. status = "okay";
  22. };
  23. };
  24. gpio-keys-polled {
  25. compatible = "gpio-keys-polled";
  26. poll-interval = <20>;
  27. reset {
  28. label = "reset";
  29. gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
  30. linux,code = <KEY_RESTART>;
  31. };
  32. };
  33. gpio-leds {
  34. compatible = "gpio-leds";
  35. led_status: status {
  36. label = "zbt-wg3526:green:status";
  37. gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
  38. };
  39. };
  40. };
  41. &sdhci {
  42. status = "okay";
  43. };
  44. &spi0 {
  45. status = "okay";
  46. m25p80@0 {
  47. compatible = "jedec,spi-nor";
  48. reg = <0>;
  49. spi-max-frequency = <10000000>;
  50. m25p,chunked-io = <32>;
  51. partitions {
  52. compatible = "fixed-partitions";
  53. #address-cells = <1>;
  54. #size-cells = <1>;
  55. partition@0 {
  56. label = "u-boot";
  57. reg = <0x0 0x30000>;
  58. read-only;
  59. };
  60. partition@30000 {
  61. label = "u-boot-env";
  62. reg = <0x30000 0x10000>;
  63. read-only;
  64. };
  65. factory: partition@40000 {
  66. label = "factory";
  67. reg = <0x40000 0x10000>;
  68. read-only;
  69. };
  70. firmware: partition@50000 {
  71. label = "firmware";
  72. };
  73. };
  74. };
  75. };
  76. &pcie {
  77. status = "okay";
  78. };
  79. &pcie0 {
  80. wifi@0,0 {
  81. compatible = "pci14c3,7603";
  82. reg = <0x0000 0 0 0 0>;
  83. mediatek,mtd-eeprom = <&factory 0x0000>;
  84. };
  85. };
  86. &pcie1 {
  87. wifi@0,0 {
  88. compatible = "pci14c3,7662";
  89. reg = <0x0000 0 0 0 0>;
  90. mediatek,mtd-eeprom = <&factory 0x8000>;
  91. ieee80211-freq-limit = <5000000 6000000>;
  92. };
  93. };
  94. &ethernet {
  95. mtd-mac-address = <&factory 0xe000>;
  96. };
  97. &pinctrl {
  98. state_default: pinctrl0 {
  99. gpio {
  100. ralink,group = "wdt", "rgmii2", "jtag", "mdio";
  101. ralink,function = "gpio";
  102. };
  103. };
  104. };