1
0

mt7620n.dtsi 7.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400
  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "ralink,mt7620n-soc";
  5. cpus {
  6. #address-cells = <1>;
  7. #size-cells = <0>;
  8. cpu@0 {
  9. compatible = "mips,mips24KEc";
  10. reg = <0>;
  11. };
  12. };
  13. chosen {
  14. bootargs = "console=ttyS0,57600";
  15. };
  16. cpuintc: cpuintc {
  17. #address-cells = <0>;
  18. #interrupt-cells = <1>;
  19. interrupt-controller;
  20. compatible = "mti,cpu-interrupt-controller";
  21. };
  22. aliases {
  23. spi0 = &spi0;
  24. spi1 = &spi1;
  25. serial0 = &uartlite;
  26. };
  27. palmbus: palmbus@10000000 {
  28. compatible = "palmbus";
  29. reg = <0x10000000 0x200000>;
  30. ranges = <0x0 0x10000000 0x1FFFFF>;
  31. #address-cells = <1>;
  32. #size-cells = <1>;
  33. sysc: sysc@0 {
  34. compatible = "ralink,mt7620a-sysc", "ralink,rt3050-sysc", "syscon";
  35. reg = <0x0 0x100>;
  36. };
  37. timer: timer@100 {
  38. compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
  39. reg = <0x100 0x20>;
  40. interrupt-parent = <&intc>;
  41. interrupts = <1>;
  42. };
  43. watchdog: watchdog@120 {
  44. compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
  45. reg = <0x120 0x10>;
  46. resets = <&rstctrl 8>;
  47. reset-names = "wdt";
  48. interrupt-parent = <&intc>;
  49. interrupts = <1>;
  50. };
  51. intc: intc@200 {
  52. compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
  53. reg = <0x200 0x100>;
  54. resets = <&rstctrl 19>;
  55. reset-names = "intc";
  56. interrupt-controller;
  57. #interrupt-cells = <1>;
  58. interrupt-parent = <&cpuintc>;
  59. interrupts = <2>;
  60. };
  61. memc: memc@300 {
  62. compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
  63. reg = <0x300 0x100>;
  64. resets = <&rstctrl 20>;
  65. reset-names = "mc";
  66. interrupt-parent = <&intc>;
  67. interrupts = <3>;
  68. };
  69. gpio0: gpio@600 {
  70. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  71. reg = <0x600 0x34>;
  72. resets = <&rstctrl 13>;
  73. reset-names = "pio";
  74. interrupt-parent = <&intc>;
  75. interrupts = <6>;
  76. gpio-controller;
  77. #gpio-cells = <2>;
  78. ralink,gpio-base = <0>;
  79. ralink,nr-gpio = <24>;
  80. ralink,register-map = [ 00 04 08 0c
  81. 20 24 28 2c
  82. 30 34 ];
  83. };
  84. gpio1: gpio@638 {
  85. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  86. reg = <0x638 0x24>;
  87. interrupt-parent = <&intc>;
  88. interrupts = <6>;
  89. gpio-controller;
  90. #gpio-cells = <2>;
  91. ralink,gpio-base = <24>;
  92. ralink,nr-gpio = <16>;
  93. ralink,register-map = [ 00 04 08 0c
  94. 10 14 18 1c
  95. 20 24 ];
  96. status = "disabled";
  97. };
  98. gpio2: gpio@660 {
  99. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  100. reg = <0x660 0x24>;
  101. interrupt-parent = <&intc>;
  102. interrupts = <6>;
  103. gpio-controller;
  104. #gpio-cells = <2>;
  105. ralink,gpio-base = <40>;
  106. ralink,nr-gpio = <32>;
  107. ralink,register-map = [ 00 04 08 0c
  108. 10 14 18 1c
  109. 20 24 ];
  110. status = "disabled";
  111. };
  112. gpio3: gpio@688 {
  113. compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
  114. reg = <0x688 0x24>;
  115. interrupt-parent = <&intc>;
  116. interrupts = <6>;
  117. gpio-controller;
  118. #gpio-cells = <2>;
  119. ralink,gpio-base = <72>;
  120. ralink,nr-gpio = <1>;
  121. ralink,register-map = [ 00 04 08 0c
  122. 10 14 18 1c
  123. 20 24 ];
  124. status = "disabled";
  125. };
  126. i2c: i2c@900 {
  127. compatible = "ralink,rt2880-i2c";
  128. reg = <0x900 0x100>;
  129. resets = <&rstctrl 16>;
  130. reset-names = "i2c";
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. status = "disabled";
  134. pinctrl-names = "default";
  135. pinctrl-0 = <&i2c_pins>;
  136. };
  137. spi0: spi@b00 {
  138. compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
  139. reg = <0xb00 0x40>;
  140. resets = <&rstctrl 18>;
  141. reset-names = "spi";
  142. #address-cells = <1>;
  143. #size-cells = <0>;
  144. status = "disabled";
  145. pinctrl-names = "default";
  146. pinctrl-0 = <&spi_pins>;
  147. };
  148. spi1: spi@b40 {
  149. compatible = "ralink,rt2880-spi";
  150. reg = <0xb40 0x60>;
  151. resets = <&rstctrl 18>;
  152. reset-names = "spi";
  153. #address-cells = <1>;
  154. #size-cells = <0>;
  155. status = "disabled";
  156. pinctrl-names = "default";
  157. pinctrl-0 = <&spi_cs1>;
  158. };
  159. uartlite: uartlite@c00 {
  160. compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
  161. reg = <0xc00 0x100>;
  162. resets = <&rstctrl 19>;
  163. reset-names = "uartl";
  164. interrupt-parent = <&intc>;
  165. interrupts = <12>;
  166. reg-shift = <2>;
  167. pinctrl-names = "default";
  168. pinctrl-0 = <&uartlite_pins>;
  169. };
  170. systick: systick@d00 {
  171. compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
  172. reg = <0xd00 0x10>;
  173. resets = <&rstctrl 28>;
  174. reset-names = "intc";
  175. interrupt-parent = <&cpuintc>;
  176. interrupts = <7>;
  177. };
  178. };
  179. pinctrl: pinctrl {
  180. compatible = "ralink,rt2880-pinmux";
  181. pinctrl-names = "default";
  182. pinctrl-0 = <&state_default>;
  183. state_default: pinctrl0 {
  184. };
  185. ephy_pins: ephy {
  186. ephy {
  187. ralink,group = "ephy";
  188. ralink,function = "ephy";
  189. };
  190. };
  191. spi_pins: spi {
  192. spi {
  193. ralink,group = "spi";
  194. ralink,function = "spi";
  195. };
  196. };
  197. spi_cs1: spi1 {
  198. spi1 {
  199. ralink,group = "spi refclk";
  200. ralink,function = "spi refclk";
  201. };
  202. };
  203. i2c_pins: i2c {
  204. i2c {
  205. ralink,group = "i2c";
  206. ralink,function = "i2c";
  207. };
  208. };
  209. uartlite_pins: uartlite {
  210. uart {
  211. ralink,group = "uartlite";
  212. ralink,function = "uartlite";
  213. };
  214. };
  215. };
  216. rstctrl: rstctrl {
  217. compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
  218. #reset-cells = <1>;
  219. };
  220. clkctrl: clkctrl {
  221. compatible = "ralink,rt2880-clock";
  222. #clock-cells = <1>;
  223. };
  224. usbphy: usbphy {
  225. compatible = "mediatek,mt7620-usbphy";
  226. #phy-cells = <0>;
  227. ralink,sysctl = <&sysc>;
  228. resets = <&rstctrl 22 &rstctrl 25>;
  229. reset-names = "host", "device";
  230. clocks = <&clkctrl 22 &clkctrl 25>;
  231. clock-names = "host", "device";
  232. };
  233. ethernet: ethernet@10100000 {
  234. compatible = "mediatek,mt7620-eth";
  235. reg = <0x10100000 0x10000>;
  236. #address-cells = <1>;
  237. #size-cells = <0>;
  238. interrupt-parent = <&cpuintc>;
  239. interrupts = <5>;
  240. resets = <&rstctrl 21 &rstctrl 23>;
  241. reset-names = "fe", "esw";
  242. mediatek,switch = <&gsw>;
  243. mdio-bus {
  244. #address-cells = <1>;
  245. #size-cells = <0>;
  246. status = "disabled";
  247. };
  248. port@4 {
  249. compatible = "mediatek,mt7620a-gsw-port", "mediatek,eth-port";
  250. reg = <4>;
  251. status = "disabled";
  252. };
  253. };
  254. gsw: gsw@10110000 {
  255. compatible = "mediatek,mt7620-gsw";
  256. reg = <0x10110000 0x8000>;
  257. resets = <&rstctrl 23>;
  258. reset-names = "esw";
  259. interrupt-parent = <&intc>;
  260. interrupts = <17>;
  261. mediatek,port4 = "ephy";
  262. };
  263. ehci: ehci@101c0000 {
  264. #address-cells = <1>;
  265. #size-cells = <0>;
  266. compatible = "generic-ehci";
  267. reg = <0x101c0000 0x1000>;
  268. interrupt-parent = <&intc>;
  269. interrupts = <18>;
  270. phys = <&usbphy>;
  271. phy-names = "usb";
  272. status = "disabled";
  273. ehci_port1: port@1 {
  274. reg = <1>;
  275. #trigger-source-cells = <0>;
  276. };
  277. };
  278. ohci: ohci@101c1000 {
  279. #address-cells = <1>;
  280. #size-cells = <0>;
  281. compatible = "generic-ohci";
  282. reg = <0x101c1000 0x1000>;
  283. phys = <&usbphy>;
  284. phy-names = "usb";
  285. interrupt-parent = <&intc>;
  286. interrupts = <18>;
  287. status = "disabled";
  288. ohci_port1: port@1 {
  289. reg = <1>;
  290. #trigger-source-cells = <0>;
  291. };
  292. };
  293. wmac: wmac@10180000 {
  294. compatible = "ralink,rt7620-wmac", "ralink,rt2880-wmac";
  295. reg = <0x10180000 0x40000>;
  296. interrupt-parent = <&cpuintc>;
  297. interrupts = <6>;
  298. ralink,eeprom = "soc_wmac.eeprom";
  299. };
  300. };