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mt7628an.dtsi 8.7 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "mediatek,mt7628an-soc";
  5. cpus {
  6. #address-cells = <1>;
  7. #size-cells = <0>;
  8. cpu@0 {
  9. compatible = "mips,mips24KEc";
  10. reg = <0>;
  11. };
  12. };
  13. chosen {
  14. bootargs = "console=ttyS0,57600";
  15. };
  16. aliases {
  17. serial0 = &uartlite;
  18. };
  19. cpuintc: cpuintc {
  20. #address-cells = <0>;
  21. #interrupt-cells = <1>;
  22. interrupt-controller;
  23. compatible = "mti,cpu-interrupt-controller";
  24. };
  25. palmbus: palmbus@10000000 {
  26. compatible = "palmbus";
  27. reg = <0x10000000 0x200000>;
  28. ranges = <0x0 0x10000000 0x1FFFFF>;
  29. #address-cells = <1>;
  30. #size-cells = <1>;
  31. sysc: sysc@0 {
  32. compatible = "ralink,mt7620a-sysc", "syscon";
  33. reg = <0x0 0x100>;
  34. };
  35. watchdog: watchdog@100 {
  36. compatible = "ralink,mt7628an-wdt", "mediatek,mt7621-wdt";
  37. reg = <0x100 0x30>;
  38. resets = <&rstctrl 8>;
  39. reset-names = "wdt";
  40. interrupt-parent = <&intc>;
  41. interrupts = <24>;
  42. };
  43. intc: intc@200 {
  44. compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
  45. reg = <0x200 0x100>;
  46. resets = <&rstctrl 9>;
  47. reset-names = "intc";
  48. interrupt-controller;
  49. #interrupt-cells = <1>;
  50. interrupt-parent = <&cpuintc>;
  51. interrupts = <2>;
  52. ralink,intc-registers = <0x9c 0xa0
  53. 0x6c 0xa4
  54. 0x80 0x78>;
  55. };
  56. memc: memc@300 {
  57. compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
  58. reg = <0x300 0x100>;
  59. resets = <&rstctrl 20>;
  60. reset-names = "mc";
  61. interrupt-parent = <&intc>;
  62. interrupts = <3>;
  63. };
  64. gpio@600 {
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
  68. reg = <0x600 0x100>;
  69. interrupt-parent = <&intc>;
  70. interrupts = <6>;
  71. gpio0: bank@0 {
  72. reg = <0>;
  73. compatible = "mtk,mt7621-gpio-bank";
  74. gpio-controller;
  75. #gpio-cells = <2>;
  76. };
  77. gpio1: bank@1 {
  78. reg = <1>;
  79. compatible = "mtk,mt7621-gpio-bank";
  80. gpio-controller;
  81. #gpio-cells = <2>;
  82. };
  83. gpio2: bank@2 {
  84. reg = <2>;
  85. compatible = "mtk,mt7621-gpio-bank";
  86. gpio-controller;
  87. #gpio-cells = <2>;
  88. };
  89. };
  90. i2c: i2c@900 {
  91. compatible = "mediatek,mt7621-i2c";
  92. reg = <0x900 0x100>;
  93. resets = <&rstctrl 16>;
  94. reset-names = "i2c";
  95. #address-cells = <1>;
  96. #size-cells = <0>;
  97. status = "disabled";
  98. pinctrl-names = "default";
  99. pinctrl-0 = <&i2c_pins>;
  100. };
  101. i2s: i2s@a00 {
  102. compatible = "mediatek,mt7628-i2s";
  103. reg = <0xa00 0x100>;
  104. resets = <&rstctrl 17>;
  105. reset-names = "i2s";
  106. interrupt-parent = <&intc>;
  107. interrupts = <10>;
  108. txdma-req = <2>;
  109. rxdma-req = <3>;
  110. dmas = <&gdma 4>,
  111. <&gdma 6>;
  112. dma-names = "tx", "rx";
  113. status = "disabled";
  114. };
  115. spi0: spi@b00 {
  116. compatible = "ralink,mt7621-spi";
  117. reg = <0xb00 0x100>;
  118. resets = <&rstctrl 18>;
  119. reset-names = "spi";
  120. #address-cells = <1>;
  121. #size-cells = <0>;
  122. pinctrl-names = "default";
  123. pinctrl-0 = <&spi_pins>;
  124. status = "disabled";
  125. };
  126. uartlite: uartlite@c00 {
  127. compatible = "ns16550a";
  128. reg = <0xc00 0x100>;
  129. reg-shift = <2>;
  130. reg-io-width = <4>;
  131. no-loopback-test;
  132. clock-frequency = <40000000>;
  133. resets = <&rstctrl 12>;
  134. reset-names = "uartl";
  135. interrupt-parent = <&intc>;
  136. interrupts = <20>;
  137. pinctrl-names = "default";
  138. pinctrl-0 = <&uart0_pins>;
  139. };
  140. uart1: uart1@d00 {
  141. compatible = "ns16550a";
  142. reg = <0xd00 0x100>;
  143. reg-shift = <2>;
  144. reg-io-width = <4>;
  145. no-loopback-test;
  146. clock-frequency = <40000000>;
  147. resets = <&rstctrl 19>;
  148. reset-names = "uart1";
  149. interrupt-parent = <&intc>;
  150. interrupts = <21>;
  151. pinctrl-names = "default";
  152. pinctrl-0 = <&uart1_pins>;
  153. status = "disabled";
  154. };
  155. uart2: uart2@e00 {
  156. compatible = "ns16550a";
  157. reg = <0xe00 0x100>;
  158. reg-shift = <2>;
  159. reg-io-width = <4>;
  160. no-loopback-test;
  161. clock-frequency = <40000000>;
  162. resets = <&rstctrl 20>;
  163. reset-names = "uart2";
  164. interrupt-parent = <&intc>;
  165. interrupts = <22>;
  166. pinctrl-names = "default";
  167. pinctrl-0 = <&uart2_pins>;
  168. status = "disabled";
  169. };
  170. pwm: pwm@5000 {
  171. compatible = "mediatek,mt7628-pwm";
  172. reg = <0x5000 0x1000>;
  173. resets = <&rstctrl 31>;
  174. reset-names = "pwm";
  175. pinctrl-names = "default";
  176. pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
  177. status = "disabled";
  178. };
  179. pcm: pcm@2000 {
  180. compatible = "ralink,mt7620a-pcm";
  181. reg = <0x2000 0x800>;
  182. resets = <&rstctrl 11>;
  183. reset-names = "pcm";
  184. interrupt-parent = <&intc>;
  185. interrupts = <4>;
  186. status = "disabled";
  187. };
  188. gdma: gdma@2800 {
  189. compatible = "ralink,rt3883-gdma";
  190. reg = <0x2800 0x800>;
  191. resets = <&rstctrl 14>;
  192. reset-names = "dma";
  193. interrupt-parent = <&intc>;
  194. interrupts = <7>;
  195. #dma-cells = <1>;
  196. #dma-channels = <16>;
  197. #dma-requests = <16>;
  198. status = "disabled";
  199. };
  200. };
  201. pinctrl: pinctrl {
  202. compatible = "ralink,rt2880-pinmux";
  203. pinctrl-names = "default";
  204. pinctrl-0 = <&state_default>;
  205. state_default: pinctrl0 {
  206. };
  207. spi_pins: spi {
  208. spi {
  209. ralink,group = "spi";
  210. ralink,function = "spi";
  211. };
  212. };
  213. spi_cs1_pins: spi_cs1 {
  214. spi_cs1 {
  215. ralink,group = "spi cs1";
  216. ralink,function = "spi cs1";
  217. };
  218. };
  219. i2c_pins: i2c {
  220. i2c {
  221. ralink,group = "i2c";
  222. ralink,function = "i2c";
  223. };
  224. };
  225. i2s_pins: i2s {
  226. i2s {
  227. ralink,group = "i2s";
  228. ralink,function = "i2s";
  229. };
  230. };
  231. uart0_pins: uartlite {
  232. uartlite {
  233. ralink,group = "uart0";
  234. ralink,function = "uart0";
  235. };
  236. };
  237. uart1_pins: uart1 {
  238. uart1 {
  239. ralink,group = "uart1";
  240. ralink,function = "uart1";
  241. };
  242. };
  243. uart2_pins: uart2 {
  244. uart2 {
  245. ralink,group = "uart2";
  246. ralink,function = "uart2";
  247. };
  248. };
  249. sdxc_pins: sdxc {
  250. sdxc {
  251. ralink,group = "sdmode";
  252. ralink,function = "sdxc";
  253. };
  254. };
  255. pwm0_pins: pwm0 {
  256. pwm0 {
  257. ralink,group = "pwm0";
  258. ralink,function = "pwm0";
  259. };
  260. };
  261. pwm1_pins: pwm1 {
  262. pwm1 {
  263. ralink,group = "pwm1";
  264. ralink,function = "pwm1";
  265. };
  266. };
  267. pcm_i2s_pins: pcm_i2s {
  268. pcm_i2s {
  269. ralink,group = "i2s";
  270. ralink,function = "pcm";
  271. };
  272. };
  273. refclk_pins: refclk {
  274. refclk {
  275. ralink,group = "refclk";
  276. ralink,function = "refclk";
  277. };
  278. };
  279. };
  280. rstctrl: rstctrl {
  281. compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
  282. #reset-cells = <1>;
  283. };
  284. clkctrl: clkctrl {
  285. compatible = "ralink,rt2880-clock";
  286. #clock-cells = <1>;
  287. };
  288. usbphy: usbphy@10120000 {
  289. compatible = "mediatek,mt7628-usbphy", "mediatek,mt7620-usbphy";
  290. reg = <0x10120000 0x1000>;
  291. #phy-cells = <0>;
  292. ralink,sysctl = <&sysc>;
  293. resets = <&rstctrl 22 &rstctrl 25>;
  294. reset-names = "host", "device";
  295. clocks = <&clkctrl 22 &clkctrl 25>;
  296. clock-names = "host", "device";
  297. };
  298. sdhci: sdhci@10130000 {
  299. compatible = "ralink,mt7620-sdhci";
  300. reg = <0x10130000 0x4000>;
  301. interrupt-parent = <&intc>;
  302. interrupts = <14>;
  303. pinctrl-names = "default";
  304. pinctrl-0 = <&sdxc_pins>;
  305. status = "disabled";
  306. };
  307. ehci: ehci@101c0000 {
  308. #address-cells = <1>;
  309. #size-cells = <0>;
  310. compatible = "generic-ehci";
  311. reg = <0x101c0000 0x1000>;
  312. phys = <&usbphy>;
  313. phy-names = "usb";
  314. interrupt-parent = <&intc>;
  315. interrupts = <18>;
  316. ehci_port1: port@1 {
  317. reg = <1>;
  318. #trigger-source-cells = <0>;
  319. };
  320. };
  321. ohci: ohci@101c1000 {
  322. #address-cells = <1>;
  323. #size-cells = <0>;
  324. compatible = "generic-ohci";
  325. reg = <0x101c1000 0x1000>;
  326. phys = <&usbphy>;
  327. phy-names = "usb";
  328. interrupt-parent = <&intc>;
  329. interrupts = <18>;
  330. ohci_port1: port@1 {
  331. reg = <1>;
  332. #trigger-source-cells = <0>;
  333. };
  334. };
  335. ethernet: ethernet@10100000 {
  336. compatible = "ralink,rt5350-eth";
  337. reg = <0x10100000 0x10000>;
  338. interrupt-parent = <&cpuintc>;
  339. interrupts = <5>;
  340. resets = <&rstctrl 21 &rstctrl 23>;
  341. reset-names = "fe", "esw";
  342. mediatek,switch = <&esw>;
  343. };
  344. esw: esw@10110000 {
  345. compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw";
  346. reg = <0x10110000 0x8000>;
  347. resets = <&rstctrl 23>;
  348. reset-names = "esw";
  349. interrupt-parent = <&intc>;
  350. interrupts = <17>;
  351. };
  352. pcie: pcie@10140000 {
  353. compatible = "mediatek,mt7620-pci";
  354. reg = <0x10140000 0x100
  355. 0x10142000 0x100>;
  356. #address-cells = <3>;
  357. #size-cells = <2>;
  358. interrupt-parent = <&cpuintc>;
  359. interrupts = <4>;
  360. resets = <&rstctrl 26 &rstctrl 27>;
  361. reset-names = "pcie0", "pcie1";
  362. clocks = <&clkctrl 26 &clkctrl 27>;
  363. clock-names = "pcie0", "pcie1";
  364. status = "disabled";
  365. device_type = "pci";
  366. bus-range = <0 255>;
  367. ranges = <
  368. 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
  369. 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
  370. >;
  371. pcie0: pcie@0,0 {
  372. reg = <0x0000 0 0 0 0>;
  373. #address-cells = <3>;
  374. #size-cells = <2>;
  375. device_type = "pci";
  376. ranges;
  377. };
  378. };
  379. wmac: wmac@10300000 {
  380. compatible = "mediatek,mt7628-wmac";
  381. reg = <0x10300000 0x100000>;
  382. interrupt-parent = <&cpuintc>;
  383. interrupts = <6>;
  384. status = "disabled";
  385. mediatek,mtd-eeprom = <&factory 0x0000>;
  386. };
  387. };