rt3050.dtsi 6.2 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
  5. cpus {
  6. #address-cells = <1>;
  7. #size-cells = <0>;
  8. cpu@0 {
  9. compatible = "mips,mips24KEc";
  10. reg = <0>;
  11. };
  12. };
  13. chosen {
  14. bootargs = "console=ttyS0,57600";
  15. };
  16. aliases {
  17. spi0 = &spi0;
  18. serial0 = &uartlite;
  19. };
  20. cpuintc: cpuintc {
  21. #address-cells = <0>;
  22. #interrupt-cells = <1>;
  23. interrupt-controller;
  24. compatible = "mti,cpu-interrupt-controller";
  25. };
  26. palmbus: palmbus@10000000 {
  27. compatible = "palmbus";
  28. reg = <0x10000000 0x200000>;
  29. ranges = <0x0 0x10000000 0x1FFFFF>;
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. sysc: sysc@0 {
  33. compatible = "ralink,rt3050-sysc", "syscon";
  34. reg = <0x0 0x100>;
  35. };
  36. timer: timer@100 {
  37. compatible = "ralink,rt3050-timer", "ralink,rt2880-timer";
  38. reg = <0x100 0x20>;
  39. interrupt-parent = <&intc>;
  40. interrupts = <1>;
  41. };
  42. watchdog: watchdog@120 {
  43. compatible = "ralink,rt3050-wdt", "ralink,rt2880-wdt";
  44. reg = <0x120 0x10>;
  45. resets = <&rstctrl 8>;
  46. reset-names = "wdt";
  47. interrupt-parent = <&intc>;
  48. interrupts = <1>;
  49. };
  50. intc: intc@200 {
  51. compatible = "ralink,rt3050-intc", "ralink,rt2880-intc";
  52. reg = <0x200 0x100>;
  53. resets = <&rstctrl 19>;
  54. reset-names = "intc";
  55. interrupt-controller;
  56. #interrupt-cells = <1>;
  57. interrupt-parent = <&cpuintc>;
  58. interrupts = <2>;
  59. };
  60. memc: memc@300 {
  61. compatible = "ralink,rt3050-memc";
  62. reg = <0x300 0x100>;
  63. resets = <&rstctrl 20>;
  64. reset-names = "mc";
  65. interrupt-parent = <&intc>;
  66. interrupts = <3>;
  67. };
  68. uart: uart@500 {
  69. compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
  70. reg = <0x500 0x100>;
  71. resets = <&rstctrl 12>;
  72. reset-names = "uart";
  73. interrupt-parent = <&intc>;
  74. interrupts = <5>;
  75. reg-shift = <2>;
  76. status = "disabled";
  77. };
  78. gpio0: gpio@600 {
  79. compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
  80. reg = <0x600 0x34>;
  81. gpio-controller;
  82. #gpio-cells = <2>;
  83. ralink,gpio-base = <0>;
  84. ralink,nr-gpio = <24>;
  85. ralink,register-map = [ 00 04 08 0c
  86. 20 24 28 2c
  87. 30 34 ];
  88. resets = <&rstctrl 13>;
  89. reset-names = "pio";
  90. interrupt-parent = <&intc>;
  91. interrupts = <6>;
  92. };
  93. gpio1: gpio@638 {
  94. compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
  95. reg = <0x638 0x24>;
  96. gpio-controller;
  97. #gpio-cells = <2>;
  98. ralink,gpio-base = <24>;
  99. ralink,nr-gpio = <16>;
  100. ralink,register-map = [ 00 04 08 0c
  101. 10 14 18 1c
  102. 20 24 ];
  103. status = "disabled";
  104. };
  105. gpio2: gpio@660 {
  106. compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
  107. reg = <0x660 0x24>;
  108. gpio-controller;
  109. #gpio-cells = <2>;
  110. ralink,gpio-base = <40>;
  111. ralink,nr-gpio = <12>;
  112. ralink,register-map = [ 00 04 08 0c
  113. 10 14 18 1c
  114. 20 24 ];
  115. status = "disabled";
  116. };
  117. gdma: gdma@700 {
  118. compatible = "ralink,rt305x-gdma";
  119. reg = <0x700 0x100>;
  120. resets = <&rstctrl 14>;
  121. reset-names = "dma";
  122. interrupt-parent = <&intc>;
  123. interrupts = <7>;
  124. #dma-cells = <1>;
  125. #dma-channels = <8>;
  126. #dma-requests = <8>;
  127. status = "disabled";
  128. };
  129. i2c@900 {
  130. compatible = "ralink,rt2880-i2c";
  131. reg = <0x900 0x100>;
  132. resets = <&rstctrl 16>;
  133. reset-names = "i2c";
  134. #address-cells = <1>;
  135. #size-cells = <0>;
  136. status = "disabled";
  137. pinctrl-names = "default";
  138. pinctrl-0 = <&i2c_pins>;
  139. };
  140. i2s@a00 {
  141. compatible = "ralink,rt3050-i2s";
  142. reg = <0xa00 0x100>;
  143. resets = <&rstctrl 17>;
  144. reset-names = "i2s";
  145. interrupt-parent = <&intc>;
  146. interrupts = <10>;
  147. txdma-req = <2>;
  148. dmas = <&gdma 4>;
  149. dma-names = "tx";
  150. status = "disabled";
  151. };
  152. spi0: spi@b00 {
  153. compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
  154. reg = <0xb00 0x100>;
  155. resets = <&rstctrl 18>;
  156. reset-names = "spi";
  157. #address-cells = <1>;
  158. #size-cells = <0>;
  159. pinctrl-names = "default";
  160. pinctrl-0 = <&spi_pins>;
  161. status = "disabled";
  162. };
  163. uartlite: uartlite@c00 {
  164. compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
  165. reg = <0xc00 0x100>;
  166. resets = <&rstctrl 19>;
  167. reset-names = "uartl";
  168. interrupt-parent = <&intc>;
  169. interrupts = <12>;
  170. reg-shift = <2>;
  171. pinctrl-names = "default";
  172. pinctrl-0 = <&uartlite_pins>;
  173. };
  174. };
  175. pinctrl: pinctrl {
  176. compatible = "ralink,rt2880-pinmux";
  177. pinctrl-names = "default";
  178. pinctrl-0 = <&state_default>;
  179. state_default: pinctrl0 {
  180. sdram {
  181. ralink,group = "sdram";
  182. ralink,function = "sdram";
  183. };
  184. };
  185. i2c_pins: i2c {
  186. i2c {
  187. ralink,group = "i2c";
  188. ralink,function = "i2c";
  189. };
  190. };
  191. spi_pins: spi {
  192. spi {
  193. ralink,group = "spi";
  194. ralink,function = "spi";
  195. };
  196. };
  197. rgmii_pins: rgmii {
  198. rgmii {
  199. ralink,group = "rgmii";
  200. ralink,function = "rgmii";
  201. };
  202. };
  203. uartlite_pins: uartlite {
  204. uart {
  205. ralink,group = "uartlite";
  206. ralink,function = "uartlite";
  207. };
  208. };
  209. };
  210. rstctrl: rstctrl {
  211. compatible = "ralink,rt3050-reset", "ralink,rt2880-reset";
  212. #reset-cells = <1>;
  213. };
  214. clkctrl: clkctrl {
  215. compatible = "ralink,rt2880-clock";
  216. #clock-cells = <1>;
  217. };
  218. usbphy: usbphy {
  219. compatible = "ralink,rt3050-usbphy";
  220. #phy-cells = <0>;
  221. ralink,sysctl = <&sysc>;
  222. resets = <&rstctrl 22>;
  223. reset-names = "host";
  224. clocks = <&clkctrl 18>;
  225. clock-names = "host";
  226. };
  227. ethernet: ethernet@10100000 {
  228. compatible = "ralink,rt3050-eth";
  229. reg = <0x10100000 0x10000>;
  230. resets = <&rstctrl 21>;
  231. reset-names = "fe";
  232. interrupt-parent = <&cpuintc>;
  233. interrupts = <5>;
  234. mediatek,switch = <&esw>;
  235. };
  236. esw: esw@10110000 {
  237. compatible = "ralink,rt3050-esw";
  238. reg = <0x10110000 0x8000>;
  239. resets = <&rstctrl 23>;
  240. reset-names = "esw";
  241. interrupt-parent = <&intc>;
  242. interrupts = <17>;
  243. };
  244. wmac: wmac@10180000 {
  245. compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
  246. reg = <0x10180000 0x40000>;
  247. interrupt-parent = <&cpuintc>;
  248. interrupts = <6>;
  249. ralink,eeprom = "soc_wmac.eeprom";
  250. };
  251. otg: otg@101c0000 {
  252. #address-cells = <1>;
  253. #size-cells = <0>;
  254. compatible = "ralink,rt3050-otg", "snps,dwc2";
  255. reg = <0x101c0000 0x40000>;
  256. interrupt-parent = <&intc>;
  257. interrupts = <18>;
  258. resets = <&rstctrl 22>;
  259. reset-names = "otg";
  260. status = "disabled";
  261. otg_port1: port@1 {
  262. reg = <1>;
  263. #trigger-source-cells = <0>;
  264. };
  265. };
  266. };