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0002-qi_lb60-add-software-usbboot-support.patch 22 KB

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  1. From fa51192b912d296b8eec10f7d44c6c17eb1dd368 Mon Sep 17 00:00:00 2001
  2. From: Xiangfu <xiangfu@openmobilefree.net>
  3. Date: Fri, 12 Oct 2012 09:47:39 +0800
  4. Subject: [PATCH 2/6] qi_lb60: add software usbboot support
  5. JZ4740 CPU have a internal ROM have such kind of code, that make
  6. JZ4740 can boot from USB
  7. usbboot.S can downloads user program from the USB port to internal
  8. SRAM and branches to the internal SRAM to execute the program
  9. Signed-off-by: Xiangfu <xiangfu@openmobilefree.net>
  10. ---
  11. board/qi/qi_lb60/Makefile | 1 +
  12. board/qi/qi_lb60/qi_lb60-spl.c | 20 +
  13. board/qi/qi_lb60/usbboot.S | 838 ++++++++++++++++++++++++++++++++++++++++
  14. 3 files changed, 859 insertions(+)
  15. create mode 100644 board/qi/qi_lb60/usbboot.S
  16. diff --git a/board/qi/qi_lb60/Makefile b/board/qi/qi_lb60/Makefile
  17. index e399246..6dd8c6f 100644
  18. --- a/board/qi/qi_lb60/Makefile
  19. +++ b/board/qi/qi_lb60/Makefile
  20. @@ -23,6 +23,7 @@ include $(TOPDIR)/config.mk
  21. LIB = $(obj)lib$(BOARD).o
  22. ifeq ($(CONFIG_SPL_BUILD),y)
  23. +SOBJS := usbboot.o
  24. COBJS := $(BOARD)-spl.o
  25. else
  26. COBJS := $(BOARD).o
  27. diff --git a/board/qi/qi_lb60/qi_lb60-spl.c b/board/qi/qi_lb60/qi_lb60-spl.c
  28. index 3fe3fa3..aea459c 100644
  29. --- a/board/qi/qi_lb60/qi_lb60-spl.c
  30. +++ b/board/qi/qi_lb60/qi_lb60-spl.c
  31. @@ -12,6 +12,24 @@
  32. #include <asm/io.h>
  33. #include <asm/jz4740.h>
  34. +#define KEY_U_OUT (32 * 2 + 16)
  35. +#define KEY_U_IN (32 * 3 + 19)
  36. +
  37. +extern void usb_boot(void);
  38. +
  39. +static void check_usb_boot(void)
  40. +{
  41. + __gpio_as_input(KEY_U_IN);
  42. + __gpio_enable_pull(KEY_U_IN);
  43. + __gpio_as_output(KEY_U_OUT);
  44. + __gpio_clear_pin(KEY_U_OUT);
  45. +
  46. + if (!__gpio_get_pin(KEY_U_IN)) {
  47. + puts("[U] pressed, goto USBBOOT mode\n");
  48. + usb_boot();
  49. + }
  50. +}
  51. +
  52. void nand_spl_boot(void)
  53. {
  54. __gpio_as_sdram_16bit_4720();
  55. @@ -23,6 +41,8 @@ void nand_spl_boot(void)
  56. pll_init();
  57. sdram_init();
  58. + check_usb_boot();
  59. +
  60. nand_init();
  61. puts("\nQi LB60 SPL: Starting U-Boot ...\n");
  62. diff --git a/board/qi/qi_lb60/usbboot.S b/board/qi/qi_lb60/usbboot.S
  63. new file mode 100644
  64. index 0000000..c872266
  65. --- /dev/null
  66. +++ b/board/qi/qi_lb60/usbboot.S
  67. @@ -0,0 +1,838 @@
  68. +/*
  69. + * for jz4740 usb boot
  70. + *
  71. + * Copyright (c) 2009 Author: <jlwei@ingenic.cn>
  72. + *
  73. + * See file CREDITS for list of people who contributed to this
  74. + * project.
  75. + *
  76. + * This program is free software; you can redistribute it and/or
  77. + * modify it under the terms of the GNU General Public License as
  78. + * published by the Free Software Foundation; either version 2 of
  79. + * the License, or (at your option) any later version.
  80. + *
  81. + * This program is distributed in the hope that it will be useful,
  82. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  83. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  84. + * GNU General Public License for more details.
  85. + *
  86. + * You should have received a copy of the GNU General Public License
  87. + * along with this program; if not, write to the Free Software
  88. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  89. + * MA 02111-1307 USA
  90. + */
  91. + .set noreorder
  92. + .globl usb_boot
  93. + .text
  94. +
  95. +/*
  96. + * Both NAND and USB boot load data to D-Cache first, then transfer
  97. + * data from D-Cache to I-Cache, and jump to execute the code in I-Cache.
  98. + * So init caches first and then dispatch to a proper boot routine.
  99. + */
  100. +
  101. +.macro load_addr reg addr
  102. + li \reg, 0x80000000
  103. + addiu \reg, \reg, \addr
  104. + la $2, usbboot_begin
  105. + subu \reg, \reg, $2
  106. +.endm
  107. +
  108. +usb_boot:
  109. + /* Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz. */
  110. + la $9, 0xB0000000 /* CPCCR: Clock Control Register */
  111. + la $8, 0x42041110 /* I:S:M:P=1:2:2:2 */
  112. + sw $8, 0($9)
  113. +
  114. + la $9, 0xB0000010 /* CPPCR: PLL Control Register */
  115. + la $8, 0x06000120 /* M=12 N=0 D=0 CLK=12*(M+2)/(N+2) */
  116. + sw $8, 0($9)
  117. +
  118. + mtc0 $0, $26 /* CP0_ERRCTL, restore WST reset state */
  119. + nop
  120. +
  121. + mtc0 $0, $16 /* CP0_CONFIG */
  122. + nop
  123. +
  124. + /* Relocate code to beginning of the ram */
  125. +
  126. + la $2, usbboot_begin
  127. + la $3, usbboot_end
  128. + li $4, 0x80000000
  129. +
  130. +1:
  131. + lw $5, 0($2)
  132. + sw $5, 0($4)
  133. + addiu $2, $2, 4
  134. + bne $2, $3, 1b
  135. + addiu $4, $4, 4
  136. +
  137. + li $2, 0x80000000
  138. + ori $3, $2, 0
  139. + addiu $3, $3, usbboot_end
  140. + la $4, usbboot_begin
  141. + subu $3, $3, $4
  142. +
  143. +
  144. +2:
  145. + cache 0x0, 0($2) /* Index_Invalidate_I */
  146. + cache 0x1, 0($2) /* Index_Writeback_Inv_D */
  147. + addiu $2, $2, 32
  148. + subu $4, $3, $2
  149. + bgtz $4, 2b
  150. + nop
  151. +
  152. + load_addr $3, usb_boot_return
  153. +
  154. + jr $3
  155. +
  156. +usbboot_begin:
  157. +
  158. +init_caches:
  159. + li $2, 3 /* cacheable for kseg0 access */
  160. + mtc0 $2, $16 /* CP0_CONFIG */
  161. + nop
  162. +
  163. + li $2, 0x20000000 /* enable idx-store-data cache insn */
  164. + mtc0 $2, $26 /* CP0_ERRCTL */
  165. +
  166. + ori $2, $28, 0 /* start address */
  167. + ori $3, $2, 0x3fe0 /* end address, total 16KB */
  168. + mtc0 $0, $28, 0 /* CP0_TAGLO */
  169. + mtc0 $0, $28, 1 /* CP0_DATALO */
  170. +cache_clear_a_line:
  171. + cache 0x8, 0($2) /* Index_Store_Tag_I */
  172. + cache 0x9, 0($2) /* Index_Store_Tag_D */
  173. + bne $2, $3, cache_clear_a_line
  174. + addiu $2, $2, 32 /* increment CACHE_LINE_SIZE */
  175. +
  176. + ori $2, $28, 0 /* start address */
  177. + ori $3, $2, 0x3fe0 /* end address, total 16KB */
  178. + la $4, 0x1ffff000 /* physical address and 4KB page mask */
  179. +cache_alloc_a_line:
  180. + and $5, $2, $4
  181. + ori $5, $5, 1 /* V bit of the physical tag */
  182. + mtc0 $5, $28, 0 /* CP0_TAGLO */
  183. + cache 0x8, 0($2) /* Index_Store_Tag_I */
  184. + cache 0x9, 0($2) /* Index_Store_Tag_D */
  185. + bne $2, $3, cache_alloc_a_line
  186. + addiu $2, $2, 32 /* increment CACHE_LINE_SIZE */
  187. +
  188. + nop
  189. + nop
  190. + nop
  191. + /*
  192. + * Transfer data from dcache to icache, then jump to icache.
  193. + * Input parameters:
  194. + * $19: data length in bytes
  195. + * $20: jump target address
  196. + */
  197. +xfer_d2i:
  198. +
  199. + ori $8, $20, 0
  200. + addu $9, $8, $19 /* total 16KB */
  201. +
  202. +1:
  203. + cache 0x0, 0($8) /* Index_Invalidate_I */
  204. + cache 0x1, 0($8) /* Index_Writeback_Inv_D */
  205. + bne $8, $9, 1b
  206. + addiu $8, $8, 32
  207. +
  208. + /* flush write-buffer */
  209. + sync
  210. +
  211. + /* Invalidate BTB */
  212. + mfc0 $8, $16, 7 /* CP0_CONFIG */
  213. + nop
  214. + ori $8, 2
  215. + mtc0 $8, $16, 7
  216. + nop
  217. +
  218. + /* Overwrite config to disable ram initalisation */
  219. + li $2, 0xff
  220. + sb $2, 20($20)
  221. +
  222. + jalr $20
  223. + nop
  224. +
  225. +icache_return:
  226. + /* User code can return to here after executing itself in
  227. + icache, by jumping to $31. */
  228. + b usb_boot_return
  229. + nop
  230. +
  231. +
  232. +usb_boot_return:
  233. + /* Enable the USB PHY */
  234. + la $9, 0xB0000024 /* CPM_SCR */
  235. + lw $8, 0($9)
  236. + ori $8, 0x40 /* USBPHY_ENABLE */
  237. + sw $8, 0($9)
  238. +
  239. + /* Initialize USB registers */
  240. + la $27, 0xb3040000 /* USB registers base address */
  241. +
  242. + sb $0, 0x0b($27) /* INTRUSBE: disable common USB interrupts */
  243. + sh $0, 0x06($27) /* INTRINE: disable EPIN interrutps */
  244. + sh $0, 0x08($27) /* INTROUTE: disable EPOUT interrutps */
  245. +
  246. + li $9, 0x61
  247. + sb $9, 0x01($27) /* POWER: HSENAB | SUSPENDM | SOFTCONN */
  248. +
  249. + /* Initialize USB states */
  250. + li $22, 0 /* set EP0 to IDLE state */
  251. + li $23, 1 /* no data stage */
  252. +
  253. + /* Main loop of polling the usb commands */
  254. +usb_command_loop:
  255. + lbu $9, 0x0a($27) /* read INTRUSB */
  256. + andi $9, 0x04 /* check USB_INTR_RESET */
  257. + beqz $9, check_intr_ep0in
  258. + nop
  259. +
  260. + /* 1. Handle USB reset interrupt */
  261. +handle_reset_intr:
  262. + lbu $9, 0x01($27) /* read POWER */
  263. + andi $9, 0x10 /* test HS_MODE */
  264. + bnez $9, _usb_set_maxpktsize
  265. + li $9, 512 /* max packet size of HS mode */
  266. + li $9, 64 /* max packet size of FS mode */
  267. +
  268. +_usb_set_maxpktsize:
  269. + li $8, 1
  270. + sb $8, 0x0e($27) /* set INDEX 1 */
  271. +
  272. + sh $9, 0x10($27) /* INMAXP */
  273. + sb $0, 0x13($27) /* INCSRH */
  274. + sh $9, 0x14($27) /* OUTMAXP */
  275. + sb $0, 0x17($27) /* OUTCSRH */
  276. +
  277. +_usb_flush_fifo:
  278. + li $8, 0x48 /* INCSR_CDT && INCSR_FF */
  279. + sb $8, 0x12($27) /* INCSR */
  280. + li $8, 0x90 /* OUTCSR_CDT && OUTCSR_FF */
  281. + sb $8, 0x16($27) /* OUTCSR */
  282. +
  283. + li $22, 0 /* set EP0 to IDLE state */
  284. + li $23, 1 /* no data stage */
  285. +
  286. + /* 2. Check and handle EP0 interrupt */
  287. +check_intr_ep0in:
  288. + lhu $10, 0x02($27) /* read INTRIN */
  289. + andi $9, $10, 0x1 /* check EP0 interrupt */
  290. + beqz $9, check_intr_ep1in
  291. + nop
  292. +
  293. +handle_ep0_intr:
  294. + sb $0, 0x0e($27) /* set INDEX 0 */
  295. + lbu $11, 0x12($27) /* read CSR0 */
  296. +
  297. + andi $9, $11, 0x04 /* check SENTSTALL */
  298. + beqz $9, _ep0_setupend
  299. + nop
  300. +
  301. +_ep0_sentstall:
  302. + andi $9, $11, 0xdb
  303. + sb $9, 0x12($27) /* clear SENDSTALL and SENTSTALL */
  304. + li $22, 0 /* set EP0 to IDLE state */
  305. +
  306. +_ep0_setupend:
  307. + andi $9, $11, 0x10 /* check SETUPEND */
  308. + beqz $9, ep0_idle_state
  309. + nop
  310. +
  311. + ori $9, $11, 0x80
  312. + sb $9, 0x12($27) /* set SVDSETUPEND */
  313. + li $22, 0 /* set EP0 to IDLE state */
  314. +
  315. +ep0_idle_state:
  316. + bnez $22, ep0_tx_state
  317. + nop
  318. +
  319. + /* 2.1 Handle EP0 IDLE state interrupt */
  320. + andi $9, $11, 0x01 /* check OUTPKTRDY */
  321. + beqz $9, check_intr_ep1in
  322. + nop
  323. +
  324. + /* Read 8-bytes setup packet from the FIFO */
  325. + lw $25, 0x20($27) /* first word of setup packet */
  326. + lw $26, 0x20($27) /* second word of setup packet */
  327. +
  328. + andi $9, $25, 0x60 /* bRequestType & USB_TYPE_MASK */
  329. + beqz $9, _ep0_std_req
  330. + nop
  331. +
  332. + /* 2.1.1 Vendor-specific setup request */
  333. +_ep0_vend_req:
  334. + li $22, 0 /* set EP0 to IDLE state */
  335. + li $23, 1 /* NoData = 1 */
  336. +
  337. + andi $9, $25, 0xff00 /* check bRequest */
  338. + srl $9, $9, 8
  339. + beqz $9, __ep0_get_cpu_info
  340. + sub $8, $9, 0x1
  341. + beqz $8, __ep0_set_data_address
  342. + sub $8, $9, 0x2
  343. + beqz $8, __ep0_set_data_length
  344. + sub $8, $9, 0x3
  345. + beqz $8, __ep0_flush_caches
  346. + sub $8, $9, 0x4
  347. + beqz $8, __ep0_prog_start1
  348. + sub $8, $9, 0x5
  349. + beqz $8, __ep0_prog_start2
  350. + nop
  351. + b _ep0_idle_state_fini /* invalid request */
  352. + nop
  353. +
  354. +__ep0_get_cpu_info:
  355. + load_addr $20, cpu_info_data /* data pointer to transfer */
  356. + li $21, 8 /* bytes left to transfer */
  357. + li $22, 1 /* set EP0 to TX state */
  358. + li $23, 0 /* NoData = 0 */
  359. +
  360. + b _ep0_idle_state_fini
  361. + nop
  362. +
  363. +__ep0_set_data_address:
  364. + li $9, 0xffff0000
  365. + and $9, $25, $9
  366. + andi $8, $26, 0xffff
  367. + or $20, $9, $8 /* data address of next transfer */
  368. +
  369. + b _ep0_idle_state_fini
  370. + nop
  371. +
  372. +__ep0_set_data_length:
  373. + li $9, 0xffff0000
  374. + and $9, $25, $9
  375. + andi $8, $26, 0xffff
  376. + or $21, $9, $8 /* data length of next transfer */
  377. +
  378. + li $9, 0x48 /* SVDOUTPKTRDY and DATAEND */
  379. + sb $9, 0x12($27) /* CSR0 */
  380. +
  381. + /* We must write packet to FIFO before EP1-IN interrupt here. */
  382. + b handle_epin1_intr
  383. + nop
  384. +
  385. +__ep0_flush_caches:
  386. + /* Flush dcache and invalidate icache. */
  387. + li $8, 0x80000000
  388. + addi $9, $8, 0x3fe0 /* total 16KB */
  389. +
  390. +1:
  391. + cache 0x0, 0($8) /* Index_Invalidate_I */
  392. + cache 0x1, 0($8) /* Index_Writeback_Inv_D */
  393. + bne $8, $9, 1b
  394. + addiu $8, $8, 32
  395. +
  396. + /* flush write-buffer */
  397. + sync
  398. +
  399. + /* Invalidate BTB */
  400. + mfc0 $8, $16, 7 /* CP0_CONFIG */
  401. + nop
  402. + ori $8, 2
  403. + mtc0 $8, $16, 7
  404. + nop
  405. +
  406. + b _ep0_idle_state_fini
  407. + nop
  408. +
  409. +__ep0_prog_start1:
  410. + li $9, 0x48 /* SVDOUTPKTRDY and DATAEND */
  411. + sb $9, 0x12($27) /* CSR0 */
  412. +
  413. + li $9, 0xffff0000
  414. + and $9, $25, $9
  415. + andi $8, $26, 0xffff
  416. + or $20, $9, $8 /* target address */
  417. +
  418. + b xfer_d2i
  419. + li $19, 0x2000 /* 16KB data length */
  420. +
  421. +__ep0_prog_start2:
  422. + li $9, 0x48 /* SVDOUTPKTRDY and DATAEND */
  423. + sb $9, 0x12($27) /* CSR0 */
  424. +
  425. + li $9, 0xffff0000
  426. + and $9, $25, $9
  427. + andi $8, $26, 0xffff
  428. + or $20, $9, $8 /* target address */
  429. +
  430. + jalr $20 /* jump, and place the return address in $31 */
  431. + nop
  432. +
  433. +__ep0_prog_start2_return:
  434. +/* User code can return to here after executing itself, by jumping to $31 */
  435. + b usb_boot_return
  436. + nop
  437. +
  438. + /* 2.1.2 Standard setup request */
  439. +_ep0_std_req:
  440. + andi $12, $25, 0xff00 /* check bRequest */
  441. + srl $12, $12, 8
  442. + sub $9, $12, 0x05 /* check USB_REQ_SET_ADDRESS */
  443. + bnez $9, __ep0_req_set_config
  444. + nop
  445. +
  446. + /* Handle USB_REQ_SET_ADDRESS */
  447. +__ep0_req_set_addr:
  448. + srl $9, $25, 16 /* get wValue */
  449. + sb $9, 0x0($27) /* set FADDR */
  450. + li $23, 1 /* NoData = 1 */
  451. + b _ep0_idle_state_fini
  452. + nop
  453. +
  454. +__ep0_req_set_config:
  455. + sub $9, $12, 0x09 /* check USB_REQ_SET_CONFIGURATION */
  456. + bnez $9, __ep0_req_get_desc
  457. + nop
  458. +
  459. + /* Handle USB_REQ_SET_CONFIGURATION */
  460. + li $23, 1 /* NoData = 1 */
  461. + b _ep0_idle_state_fini
  462. + nop
  463. +
  464. +__ep0_req_get_desc:
  465. + sub $9, $12, 0x06 /* check USB_REQ_GET_DESCRIPTOR */
  466. + bnez $9, _ep0_idle_state_fini
  467. + li $23, 1 /* NoData = 1 */
  468. +
  469. + /* Handle USB_REQ_GET_DESCRIPTOR */
  470. + li $23, 0 /* NoData = 0 */
  471. +
  472. + srl $9, $25, 24 /* wValue >> 8 */
  473. + sub $8, $9, 0x01 /* check USB_DT_DEVICE */
  474. + beqz $8, ___ep0_get_dev_desc
  475. + srl $21, $26, 16 /* get wLength */
  476. + sub $8, $9, 0x02 /* check USB_DT_CONFIG */
  477. + beqz $8, ___ep0_get_conf_desc
  478. + sub $8, $9, 0x03 /* check USB_DT_STRING */
  479. + beqz $8, ___ep0_get_string_desc
  480. + sub $8, $9, 0x06 /* check USB_DT_DEVICE_QUALIFIER */
  481. + beqz $8, ___ep0_get_dev_qualifier
  482. + nop
  483. + b _ep0_idle_state_fini
  484. + nop
  485. +
  486. +___ep0_get_dev_desc:
  487. + load_addr $20, device_desc /* data pointer */
  488. + li $22, 1 /* set EP0 to TX state */
  489. + sub $8, $21, 18
  490. + blez $8, _ep0_idle_state_fini /* wLength <= 18 */
  491. + nop
  492. + li $21, 18 /* max length of device_desc */
  493. + b _ep0_idle_state_fini
  494. + nop
  495. +
  496. +___ep0_get_dev_qualifier:
  497. + load_addr $20, dev_qualifier /* data pointer */
  498. + li $22, 1 /* set EP0 to TX state */
  499. + sub $8, $21, 10
  500. + blez $8, _ep0_idle_state_fini /* wLength <= 10 */
  501. + nop
  502. + li $21, 10 /* max length of dev_qualifier */
  503. + b _ep0_idle_state_fini
  504. + nop
  505. +
  506. +___ep0_get_conf_desc:
  507. + load_addr $20, config_desc_fs /* data pointer of FS mode */
  508. + lbu $8, 0x01($27) /* read POWER */
  509. + andi $8, 0x10 /* test HS_MODE */
  510. + beqz $8, ___ep0_get_conf_desc2
  511. + nop
  512. + load_addr $20, config_desc_hs /* data pointer of HS mode */
  513. +
  514. +___ep0_get_conf_desc2:
  515. + li $22, 1 /* set EP0 to TX state */
  516. + sub $8, $21, 32
  517. + blez $8, _ep0_idle_state_fini /* wLength <= 32 */
  518. + nop
  519. + li $21, 32 /* max length of config_desc */
  520. + b _ep0_idle_state_fini
  521. + nop
  522. +
  523. +___ep0_get_string_desc:
  524. + li $22, 1 /* set EP0 to TX state */
  525. +
  526. + srl $9, $25, 16 /* wValue & 0xff */
  527. + andi $9, 0xff
  528. +
  529. + sub $8, $9, 1
  530. + beqz $8, ___ep0_get_string_manufacture
  531. + sub $8, $9, 2
  532. + beqz $8, ___ep0_get_string_product
  533. + nop
  534. +
  535. +___ep0_get_string_lang_ids:
  536. + load_addr $20, string_lang_ids /* data pointer */
  537. + b _ep0_idle_state_fini
  538. + li $21, 4 /* data length */
  539. +
  540. +___ep0_get_string_manufacture:
  541. + load_addr $20, string_manufacture /* data pointer */
  542. + b _ep0_idle_state_fini
  543. + li $21, 16 /* data length */
  544. +
  545. +___ep0_get_string_product:
  546. + load_addr $20, string_product /* data pointer */
  547. + b _ep0_idle_state_fini
  548. + li $21, 46 /* data length */
  549. +
  550. +_ep0_idle_state_fini:
  551. + li $9, 0x40 /* SVDOUTPKTRDY */
  552. + beqz $23, _ep0_idle_state_fini2
  553. + nop
  554. + ori $9, $9, 0x08 /* DATAEND */
  555. +_ep0_idle_state_fini2:
  556. + sb $9, 0x12($27) /* CSR0 */
  557. + beqz $22, check_intr_ep1in
  558. + nop
  559. +
  560. + /* 2.2 Handle EP0 TX state interrupt */
  561. +ep0_tx_state:
  562. + sub $9, $22, 1
  563. + bnez $9, check_intr_ep1in
  564. + nop
  565. +
  566. + sub $9, $21, 64 /* max packetsize */
  567. + blez $9, _ep0_tx_state2 /* data count <= 64 */
  568. + ori $19, $21, 0
  569. + li $19, 64
  570. +
  571. +_ep0_tx_state2:
  572. + beqz $19, _ep0_tx_state3 /* send ZLP */
  573. + ori $18, $19, 0 /* record bytes to be transferred */
  574. + sub $21, $21, $19 /* decrement data count */
  575. +
  576. +_ep0_fifo_write_loop:
  577. + lbu $9, 0($20) /* read data */
  578. + sb $9, 0x20($27) /* load FIFO */
  579. + sub $19, $19, 1 /* decrement counter */
  580. + bnez $19, _ep0_fifo_write_loop
  581. + addi $20, $20, 1 /* increment data pointer */
  582. +
  583. + sub $9, $18, 64 /* max packetsize */
  584. + beqz $9, _ep0_tx_state4
  585. + nop
  586. +
  587. +_ep0_tx_state3:
  588. + /* transferred bytes < max packetsize */
  589. + li $9, 0x0a /* set INPKTRDY and DATAEND */
  590. + sb $9, 0x12($27) /* CSR0 */
  591. + li $22, 0 /* set EP0 to IDLE state */
  592. + b check_intr_ep1in
  593. + nop
  594. +
  595. +_ep0_tx_state4:
  596. + /* transferred bytes == max packetsize */
  597. + li $9, 0x02 /* set INPKTRDY */
  598. + sb $9, 0x12($27) /* CSR0 */
  599. + b check_intr_ep1in
  600. + nop
  601. +
  602. + /* 3. Check and handle EP1 BULK-IN interrupt */
  603. +check_intr_ep1in:
  604. + andi $9, $10, 0x2 /* check EP1 IN interrupt */
  605. + beqz $9, check_intr_ep1out
  606. + nop
  607. +
  608. +handle_epin1_intr:
  609. + li $9, 1
  610. + sb $9, 0x0e($27) /* set INDEX 1 */
  611. + lbu $9, 0x12($27) /* read INCSR */
  612. +
  613. + andi $8, $9, 0x2 /* check INCSR_FFNOTEMPT */
  614. + bnez $8, _epin1_tx_state4
  615. + nop
  616. +
  617. +_epin1_write_fifo:
  618. + lhu $9, 0x10($27) /* get INMAXP */
  619. + sub $8, $21, $9
  620. + blez $8, _epin1_tx_state1 /* bytes left <= INMAXP */
  621. + ori $19, $21, 0
  622. + ori $19, $9, 0
  623. +
  624. +_epin1_tx_state1:
  625. + beqz $19, _epin1_tx_state4 /* No data */
  626. + nop
  627. +
  628. + sub $21, $21, $19 /* decrement data count */
  629. +
  630. + srl $5, $19, 2 /* # of word */
  631. + andi $6, $19, 0x3 /* # of byte */
  632. + beqz $5, _epin1_tx_state2
  633. + nop
  634. +
  635. +_epin1_fifo_write_word:
  636. + lw $9, 0($20) /* read data from source address */
  637. + sw $9, 0x24($27) /* write FIFO */
  638. + sub $5, $5, 1 /* decrement counter */
  639. + bnez $5, _epin1_fifo_write_word
  640. + addiu $20, $20, 4 /* increment dest address */
  641. +
  642. +_epin1_tx_state2:
  643. + beqz $6, _epin1_tx_state3
  644. + nop
  645. +
  646. +_epin1_fifo_write_byte:
  647. + lbu $9, 0($20) /* read data from source address */
  648. + sb $9, 0x24($27) /* write FIFO */
  649. + sub $6, $6, 1 /* decrement counter */
  650. + bnez $6, _epin1_fifo_write_byte
  651. + addiu $20, $20, 1 /* increment dest address */
  652. +
  653. +_epin1_tx_state3:
  654. + li $9, 0x1
  655. + sb $9, 0x12($27) /* INCSR, set INPKTRDY */
  656. +
  657. +_epin1_tx_state4:
  658. + /* 4. Check and handle EP1 BULK-OUT interrupt */
  659. +check_intr_ep1out:
  660. + lhu $9, 0x04($27) /* read INTROUT */
  661. + andi $9, 0x2
  662. + beqz $9, check_status_next
  663. + nop
  664. +
  665. +handle_epout1_intr:
  666. + li $9, 1
  667. + sb $9, 0x0e($27) /* set INDEX 1 */
  668. +
  669. + lbu $9, 0x16($27) /* read OUTCSR */
  670. + andi $9, 0x1 /* check OUTPKTRDY */
  671. + beqz $9, check_status_next
  672. + nop
  673. +
  674. +_epout1_read_fifo:
  675. + lhu $19, 0x18($27) /* read OUTCOUNT */
  676. + srl $5, $19, 2 /* # of word */
  677. + andi $6, $19, 0x3 /* # of byte */
  678. + beqz $5, _epout1_rx_state1
  679. + nop
  680. +
  681. +_epout1_fifo_read_word:
  682. + lw $9, 0x24($27) /* read FIFO */
  683. + sw $9, 0($20) /* store to dest address */
  684. + sub $5, $5, 1 /* decrement counter */
  685. + bnez $5, _epout1_fifo_read_word
  686. + addiu $20, $20, 4 /* increment dest address */
  687. +
  688. +_epout1_rx_state1:
  689. + beqz $6, _epout1_rx_state2
  690. + nop
  691. +
  692. +_epout1_fifo_read_byte:
  693. + lbu $9, 0x24($27) /* read FIFO */
  694. + sb $9, 0($20) /* store to dest address */
  695. + sub $6, $6, 1 /* decrement counter */
  696. + bnez $6, _epout1_fifo_read_byte
  697. + addiu $20, $20, 1 /* increment dest address */
  698. +
  699. +_epout1_rx_state2:
  700. + sb $0, 0x16($27) /* clear OUTPKTRDY */
  701. +
  702. +check_status_next:
  703. + b usb_command_loop
  704. + nop
  705. +
  706. +/* Device/Configuration/Interface/Endpoint/String Descriptors */
  707. +
  708. + .align 2
  709. +device_desc:
  710. + .byte 0x12 /* bLength */
  711. + .byte 0x01 /* bDescriptorType */
  712. + .byte 0x00 /* bcdUSB */
  713. + .byte 0x02 /* bcdUSB */
  714. + .byte 0x00 /* bDeviceClass */
  715. + .byte 0x00 /* bDeviceSubClass */
  716. + .byte 0x00 /* bDeviceProtocol */
  717. + .byte 0x40 /* bMaxPacketSize0 */
  718. + .byte 0x1a /* idVendor */
  719. + .byte 0x60 /* idVendor */
  720. + .byte 0x40 /* idProduct */
  721. + .byte 0x47 /* idProduct */
  722. + .byte 0x00 /* bcdDevice */
  723. + .byte 0x01 /* bcdDevice */
  724. + .byte 0x01 /* iManufacturer */
  725. + .byte 0x02 /* iProduct */
  726. + .byte 0x00 /* iSerialNumber */
  727. + .byte 0x01 /* bNumConfigurations */
  728. +
  729. + .align 2
  730. +dev_qualifier:
  731. + .byte 0x0a /* bLength */
  732. + .byte 0x06 /* bDescriptorType */
  733. + .byte 0x00 /* bcdUSB */
  734. + .byte 0x02 /* bcdUSB */
  735. + .byte 0x00 /* bDeviceClass */
  736. + .byte 0x00 /* bDeviceSubClass */
  737. + .byte 0x00 /* bDeviceProtocol */
  738. + .byte 0x40 /* bMaxPacketSize0 */
  739. + .byte 0x01 /* bNumConfigurations */
  740. + .byte 0x00 /* bRESERVED */
  741. +
  742. + .align 2
  743. +config_desc_hs:
  744. + .byte 0x09 /* bLength */
  745. + .byte 0x02 /* bDescriptorType */
  746. + .byte 0x20 /* wTotalLength */
  747. + .byte 0x00 /* wTotalLength */
  748. + .byte 0x01 /* bNumInterfaces */
  749. + .byte 0x01 /* bConfigurationValue */
  750. + .byte 0x00 /* iConfiguration */
  751. + .byte 0xc0 /* bmAttributes */
  752. + .byte 0x01 /* MaxPower */
  753. +intf_desc_hs:
  754. + .byte 0x09 /* bLength */
  755. + .byte 0x04 /* bDescriptorType */
  756. + .byte 0x00 /* bInterfaceNumber */
  757. + .byte 0x00 /* bAlternateSetting */
  758. + .byte 0x02 /* bNumEndpoints */
  759. + .byte 0xff /* bInterfaceClass */
  760. + .byte 0x00 /* bInterfaceSubClass */
  761. + .byte 0x50 /* bInterfaceProtocol */
  762. + .byte 0x00 /* iInterface */
  763. +ep1_desc_hs:
  764. + .byte 0x07 /* bLength */
  765. + .byte 0x05 /* bDescriptorType */
  766. + .byte 0x01 /* bEndpointAddress */
  767. + .byte 0x02 /* bmAttributes */
  768. + .byte 0x00 /* wMaxPacketSize */
  769. + .byte 0x02 /* wMaxPacketSize */
  770. + .byte 0x00 /* bInterval */
  771. +ep2_desc_hs:
  772. + .byte 0x07 /* bLength */
  773. + .byte 0x05 /* bDescriptorType */
  774. + .byte 0x81 /* bEndpointAddress */
  775. + .byte 0x02 /* bmAttributes */
  776. + .byte 0x00 /* wMaxPacketSize */
  777. + .byte 0x02 /* wMaxPacketSize */
  778. + .byte 0x00 /* bInterval */
  779. +
  780. + .align 2
  781. +config_desc_fs:
  782. + .byte 0x09 /* bLength */
  783. + .byte 0x02 /* bDescriptorType */
  784. + .byte 0x20 /* wTotalLength */
  785. + .byte 0x00 /* wTotalLength */
  786. + .byte 0x01 /* bNumInterfaces */
  787. + .byte 0x01 /* bConfigurationValue */
  788. + .byte 0x00 /* iConfiguration */
  789. + .byte 0xc0 /* bmAttributes */
  790. + .byte 0x01 /* MaxPower */
  791. +intf_desc_fs:
  792. + .byte 0x09 /* bLength */
  793. + .byte 0x04 /* bDescriptorType */
  794. + .byte 0x00 /* bInterfaceNumber */
  795. + .byte 0x00 /* bAlternateSetting */
  796. + .byte 0x02 /* bNumEndpoints */
  797. + .byte 0xff /* bInterfaceClass */
  798. + .byte 0x00 /* bInterfaceSubClass */
  799. + .byte 0x50 /* bInterfaceProtocol */
  800. + .byte 0x00 /* iInterface */
  801. +ep1_desc_fs:
  802. + .byte 0x07 /* bLength */
  803. + .byte 0x05 /* bDescriptorType */
  804. + .byte 0x01 /* bEndpointAddress */
  805. + .byte 0x02 /* bmAttributes */
  806. + .byte 0x40 /* wMaxPacketSize */
  807. + .byte 0x00 /* wMaxPacketSize */
  808. + .byte 0x00 /* bInterval */
  809. +ep2_desc_fs:
  810. + .byte 0x07 /* bLength */
  811. + .byte 0x05 /* bDescriptorType */
  812. + .byte 0x81 /* bEndpointAddress */
  813. + .byte 0x02 /* bmAttributes */
  814. + .byte 0x40 /* wMaxPacketSize */
  815. + .byte 0x00 /* wMaxPacketSize */
  816. + .byte 0x00 /* bInterval */
  817. +
  818. + .align 2
  819. +string_lang_ids:
  820. + .byte 0x04
  821. + .byte 0x03
  822. + .byte 0x09
  823. + .byte 0x04
  824. +
  825. + .align 2
  826. +string_manufacture:
  827. + .byte 0x10
  828. + .byte 0x03
  829. + .byte 0x49
  830. + .byte 0x00
  831. + .byte 0x6e
  832. + .byte 0x00
  833. + .byte 0x67
  834. + .byte 0x00
  835. + .byte 0x65
  836. + .byte 0x00
  837. + .byte 0x6e
  838. + .byte 0x00
  839. + .byte 0x69
  840. + .byte 0x00
  841. + .byte 0x63
  842. + .byte 0x00
  843. +
  844. + .align 2
  845. +string_product:
  846. + .byte 0x2e
  847. + .byte 0x03
  848. + .byte 0x4a
  849. + .byte 0x00
  850. + .byte 0x5a
  851. + .byte 0x00
  852. + .byte 0x34
  853. + .byte 0x00
  854. + .byte 0x37
  855. + .byte 0x00
  856. + .byte 0x34
  857. + .byte 0x00
  858. + .byte 0x30
  859. + .byte 0x00
  860. + .byte 0x20
  861. + .byte 0x00
  862. + .byte 0x55
  863. + .byte 0x00
  864. + .byte 0x53
  865. + .byte 0x00
  866. + .byte 0x42
  867. + .byte 0x00
  868. + .byte 0x20
  869. + .byte 0x00
  870. + .byte 0x42
  871. + .byte 0x00
  872. + .byte 0x6f
  873. + .byte 0x00
  874. + .byte 0x6f
  875. + .byte 0x00
  876. + .byte 0x74
  877. + .byte 0x00
  878. + .byte 0x20
  879. + .byte 0x00
  880. + .byte 0x44
  881. + .byte 0x00
  882. + .byte 0x65
  883. + .byte 0x00
  884. + .byte 0x76
  885. + .byte 0x00
  886. + .byte 0x69
  887. + .byte 0x00
  888. + .byte 0x63
  889. + .byte 0x00
  890. + .byte 0x65
  891. + .byte 0x00
  892. +
  893. + .align 2
  894. +cpu_info_data:
  895. + .byte 0x4a
  896. + .byte 0x5a
  897. + .byte 0x34
  898. + .byte 0x37
  899. + .byte 0x34
  900. + .byte 0x30
  901. + .byte 0x56
  902. + .byte 0x31
  903. +usbboot_end:
  904. +
  905. + .set reorder
  906. --
  907. 1.7.9.5