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0005-add-nanonote-lcd-support.patch 26 KB

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  1. From ca8c5216cfd3ad3fda9867ed2d157ae5a209834b Mon Sep 17 00:00:00 2001
  2. From: Xiangfu <xiangfu@openmobilefree.net>
  3. Date: Wed, 10 Oct 2012 22:05:27 +0800
  4. Subject: [PATCH 5/6] add nanonote lcd support
  5. ---
  6. arch/mips/include/asm/global_data.h | 1 +
  7. arch/mips/include/asm/jz4740.h | 90 ++++++++
  8. arch/mips/lib/board.c | 6 +
  9. common/lcd.c | 9 +-
  10. drivers/video/Makefile | 1 +
  11. drivers/video/nanonote_gpm940b0.c | 400 +++++++++++++++++++++++++++++++++++
  12. drivers/video/nanonote_gpm940b0.h | 135 ++++++++++++
  13. include/configs/qi_lb60.h | 7 +
  14. include/lcd.h | 52 ++++-
  15. 9 files changed, 697 insertions(+), 4 deletions(-)
  16. create mode 100644 drivers/video/nanonote_gpm940b0.c
  17. create mode 100644 drivers/video/nanonote_gpm940b0.h
  18. diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
  19. index cd03d7e..7cec2de 100644
  20. --- a/arch/mips/include/asm/global_data.h
  21. +++ b/arch/mips/include/asm/global_data.h
  22. @@ -44,6 +44,7 @@ typedef struct global_data {
  23. unsigned long per_clk; /* Peripheral bus clock */
  24. unsigned long mem_clk; /* Memory bus clock */
  25. unsigned long dev_clk; /* Device clock */
  26. + unsigned long fb_base; /* base address of framebuffer */
  27. /* "static data" needed by most of timer.c */
  28. unsigned long tbl;
  29. unsigned long lastinc;
  30. diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h
  31. index 68287fb..13724a2 100644
  32. --- a/arch/mips/include/asm/jz4740.h
  33. +++ b/arch/mips/include/asm/jz4740.h
  34. @@ -1312,5 +1312,95 @@ do { \
  35. while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
  36. } while (0)
  37. +/*************************************************************************
  38. + * LCD (LCD Controller)
  39. + *************************************************************************/
  40. +#define REG32(addr) *((volatile u32 *)(addr))
  41. +
  42. +#define CPM_BASE 0xB0000000
  43. +#define CPM_CPCCR (CPM_BASE+0x00)
  44. +#define REG_CPM_CPCCR REG32(CPM_CPCCR)
  45. +
  46. +#define LCD_BASE 0xB3050000
  47. +#define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
  48. +#define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
  49. +#define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
  50. +#define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
  51. +#define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
  52. +#define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
  53. +#define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
  54. +#define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
  55. +#define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
  56. +#define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
  57. +#define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
  58. +#define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
  59. +#define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
  60. +#define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
  61. +#define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
  62. +#define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
  63. +#define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
  64. +#define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
  65. +#define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
  66. +#define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
  67. +#define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
  68. +
  69. +#define REG_LCD_CFG REG32(LCD_CFG)
  70. +#define REG_LCD_VSYNC REG32(LCD_VSYNC)
  71. +#define REG_LCD_HSYNC REG32(LCD_HSYNC)
  72. +#define REG_LCD_VAT REG32(LCD_VAT)
  73. +#define REG_LCD_DAH REG32(LCD_DAH)
  74. +#define REG_LCD_DAV REG32(LCD_DAV)
  75. +#define REG_LCD_PS REG32(LCD_PS)
  76. +#define REG_LCD_CLS REG32(LCD_CLS)
  77. +#define REG_LCD_SPL REG32(LCD_SPL)
  78. +#define REG_LCD_REV REG32(LCD_REV)
  79. +#define REG_LCD_CTRL REG32(LCD_CTRL)
  80. +#define REG_LCD_STATE REG32(LCD_STATE)
  81. +#define REG_LCD_IID REG32(LCD_IID)
  82. +#define REG_LCD_DA0 REG32(LCD_DA0)
  83. +#define REG_LCD_SA0 REG32(LCD_SA0)
  84. +#define REG_LCD_FID0 REG32(LCD_FID0)
  85. +#define REG_LCD_CMD0 REG32(LCD_CMD0)
  86. +#define REG_LCD_DA1 REG32(LCD_DA1)
  87. +#define REG_LCD_SA1 REG32(LCD_SA1)
  88. +#define REG_LCD_FID1 REG32(LCD_FID1)
  89. +#define REG_LCD_CMD1 REG32(LCD_CMD1)
  90. +
  91. +#define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
  92. +#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
  93. + #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
  94. + #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
  95. + #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
  96. + #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
  97. + #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
  98. + #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
  99. +
  100. +#define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
  101. +#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
  102. + #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
  103. + #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
  104. + #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
  105. +#define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
  106. +#define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
  107. +#define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
  108. +#define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
  109. +#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
  110. + #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
  111. + #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
  112. + #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
  113. +
  114. +#define CPM_LPCDR (CPM_BASE+0x64)
  115. +#define CPM_CLKGR (CPM_BASE+0x20)
  116. +#define REG_CPM_LPCDR REG32(CPM_LPCDR)
  117. +#define REG_CPM_CLKGR REG32(CPM_CLKGR)
  118. +
  119. +#define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
  120. +#define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
  121. +#define __cpm_set_pixdiv(v) \
  122. + (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
  123. +#define __cpm_set_ldiv(v) \
  124. + (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
  125. +#define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
  126. +
  127. #endif /* !__ASSEMBLY__ */
  128. #endif /* __JZ4740_H__ */
  129. diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
  130. index b14b33e..c2e64d9 100644
  131. --- a/arch/mips/lib/board.c
  132. +++ b/arch/mips/lib/board.c
  133. @@ -172,6 +172,12 @@ void board_init_f(ulong bootflag)
  134. addr &= ~(4096 - 1);
  135. debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
  136. +#ifdef CONFIG_LCD
  137. + /* reserve memory for LCD display (always full pages) */
  138. + addr = lcd_setmem (addr);
  139. + gd->fb_base = addr;
  140. +#endif /* CONFIG_LCD */
  141. +
  142. /* Reserve memory for U-Boot code, data & bss
  143. * round down to next 16 kB limit
  144. */
  145. diff --git a/common/lcd.c b/common/lcd.c
  146. index b6be800..af1281a 100644
  147. --- a/common/lcd.c
  148. +++ b/common/lcd.c
  149. @@ -263,6 +263,13 @@ static void lcd_drawchars(ushort x, ushort y, uchar *str, int count)
  150. lcd_color_fg : lcd_color_bg;
  151. bits <<= 1;
  152. }
  153. +#elif LCD_BPP == LCD_COLOR32
  154. + uint *m = (uint *)d;
  155. + for (c=0; c<32; ++c) {
  156. + *m++ = (bits & 0x80) ?
  157. + lcd_color_fg : lcd_color_bg;
  158. + bits <<= 1;
  159. + }
  160. #endif
  161. }
  162. #if LCD_BPP == LCD_MONOCHROME
  163. @@ -509,7 +516,7 @@ static inline ushort *configuration_get_cmap(void)
  164. return (ushort *)&(cp->lcd_cmap[255 * sizeof(ushort)]);
  165. #elif defined(CONFIG_ATMEL_LCD)
  166. return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
  167. -#elif !defined(CONFIG_ATMEL_HLCD) && !defined(CONFIG_EXYNOS_FB)
  168. +#elif !defined(CONFIG_ATMEL_HLCD) && !defined(CONFIG_EXYNOS_FB) && !defined(CONFIG_VIDEO_GPM940B0)
  169. return panel_info.cmap;
  170. #else
  171. #if defined(CONFIG_LCD_LOGO)
  172. diff --git a/drivers/video/Makefile b/drivers/video/Makefile
  173. index ebb6da8..03625bc 100644
  174. --- a/drivers/video/Makefile
  175. +++ b/drivers/video/Makefile
  176. @@ -50,6 +50,7 @@ COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
  177. COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
  178. COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
  179. COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
  180. +COBJS-$(CONFIG_VIDEO_GPM940B0) += nanonote_gpm940b0.o
  181. COBJS := $(sort $(COBJS-y))
  182. SRCS := $(COBJS:.o=.c)
  183. diff --git a/drivers/video/nanonote_gpm940b0.c b/drivers/video/nanonote_gpm940b0.c
  184. new file mode 100644
  185. index 0000000..11efb72
  186. --- /dev/null
  187. +++ b/drivers/video/nanonote_gpm940b0.c
  188. @@ -0,0 +1,400 @@
  189. +/*
  190. + * JzRISC lcd controller
  191. + *
  192. + * Xiangfu Liu <xiangfu@sharism.cc>
  193. + *
  194. + * This program is free software; you can redistribute it and/or
  195. + * modify it under the terms of the GNU General Public License as
  196. + * published by the Free Software Foundation; either version 2 of
  197. + * the License, or (at your option) any later version.
  198. + *
  199. + * This program is distributed in the hope that it will be useful,
  200. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  201. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  202. + * GNU General Public License for more details.
  203. + *
  204. + * You should have received a copy of the GNU General Public License
  205. + * along with this program; if not, write to the Free Software
  206. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  207. + * MA 02111-1307 USA
  208. + */
  209. +
  210. +#include <config.h>
  211. +#include <common.h>
  212. +#include <lcd.h>
  213. +
  214. +#include <asm/io.h> /* virt_to_phys() */
  215. +#include <asm/jz4740.h>
  216. +
  217. +#include "nanonote_gpm940b0.h"
  218. +
  219. +#define align2(n) (n)=((((n)+1)>>1)<<1)
  220. +#define align4(n) (n)=((((n)+3)>>2)<<2)
  221. +#define align8(n) (n)=((((n)+7)>>3)<<3)
  222. +
  223. +struct jzfb_info {
  224. + unsigned int cfg; /* panel mode and pin usage etc. */
  225. + unsigned int w;
  226. + unsigned int h;
  227. + unsigned int bpp; /* bit per pixel */
  228. + unsigned int fclk; /* frame clk */
  229. + unsigned int hsw; /* hsync width, in pclk */
  230. + unsigned int vsw; /* vsync width, in line count */
  231. + unsigned int elw; /* end of line, in pclk */
  232. + unsigned int blw; /* begin of line, in pclk */
  233. + unsigned int efw; /* end of frame, in line count */
  234. + unsigned int bfw; /* begin of frame, in line count */
  235. +};
  236. +
  237. +static struct jzfb_info jzfb = {
  238. + MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
  239. + 320, 240, 32, 70, 1, 1, 273, 140, 1, 20
  240. +};
  241. +
  242. +vidinfo_t panel_info = {
  243. + 320, 240, LCD_BPP,
  244. +};
  245. +
  246. +void *lcd_base;
  247. +void *lcd_console_address;
  248. +int lcd_line_length;
  249. +int lcd_color_fg;
  250. +int lcd_color_bg;
  251. +short console_col;
  252. +short console_row;
  253. +
  254. +static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
  255. +{
  256. + u_long palette_mem_size;
  257. + struct jz_fb_info *fbi = &vid->jz_fb;
  258. + int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
  259. +
  260. + fbi->screen = (u_long)lcdbase;
  261. + fbi->palette_size = 256;
  262. + palette_mem_size = fbi->palette_size * sizeof(u16);
  263. +
  264. + debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
  265. + /* locate palette and descs at end of page following fb */
  266. + fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
  267. +
  268. + return 0;
  269. +}
  270. +
  271. +static void jz_lcd_desc_init(vidinfo_t *vid)
  272. +{
  273. + struct jz_fb_info * fbi;
  274. + fbi = &vid->jz_fb;
  275. + fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
  276. + fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
  277. + fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
  278. +
  279. + #define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
  280. +
  281. + /* populate descriptors */
  282. + fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
  283. + fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
  284. + fbi->dmadesc_fblow->fidr = 0;
  285. + fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
  286. +
  287. + fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
  288. +
  289. + fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
  290. + fbi->dmadesc_fbhigh->fidr = 0;
  291. + fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
  292. +
  293. + fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
  294. + fbi->dmadesc_palette->fidr = 0;
  295. + fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
  296. +
  297. + if(NBITS(vid->vl_bpix) < 12) {
  298. + /* assume any mode with <12 bpp is palette driven */
  299. + fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
  300. + fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
  301. + /* flips back and forth between pal and fbhigh */
  302. + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
  303. + } else {
  304. + /* palette shouldn't be loaded in true-color mode */
  305. + fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
  306. + fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
  307. + }
  308. +}
  309. +
  310. +static int jz_lcd_hw_init(vidinfo_t *vid)
  311. +{
  312. + struct jz_fb_info *fbi = &vid->jz_fb;
  313. + unsigned int val = 0;
  314. + unsigned int pclk;
  315. + unsigned int stnH;
  316. + int pll_div;
  317. +
  318. + /* Setting Control register */
  319. + switch (jzfb.bpp) {
  320. + case 1:
  321. + val |= LCD_CTRL_BPP_1;
  322. + break;
  323. + case 2:
  324. + val |= LCD_CTRL_BPP_2;
  325. + break;
  326. + case 4:
  327. + val |= LCD_CTRL_BPP_4;
  328. + break;
  329. + case 8:
  330. + val |= LCD_CTRL_BPP_8;
  331. + break;
  332. + case 15:
  333. + val |= LCD_CTRL_RGB555;
  334. + case 16:
  335. + val |= LCD_CTRL_BPP_16;
  336. + break;
  337. + case 17 ... 32:
  338. + val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
  339. + break;
  340. +
  341. + default:
  342. + printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
  343. + val |= LCD_CTRL_BPP_16;
  344. + break;
  345. + }
  346. +
  347. + switch (jzfb.cfg & MODE_MASK) {
  348. + case MODE_STN_MONO_DUAL:
  349. + case MODE_STN_COLOR_DUAL:
  350. + case MODE_STN_MONO_SINGLE:
  351. + case MODE_STN_COLOR_SINGLE:
  352. + switch (jzfb.bpp) {
  353. + case 1:
  354. + /* val |= LCD_CTRL_PEDN; */
  355. + case 2:
  356. + val |= LCD_CTRL_FRC_2;
  357. + break;
  358. + case 4:
  359. + val |= LCD_CTRL_FRC_4;
  360. + break;
  361. + case 8:
  362. + default:
  363. + val |= LCD_CTRL_FRC_16;
  364. + break;
  365. + }
  366. + break;
  367. + }
  368. +
  369. + val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
  370. + val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
  371. +
  372. + switch (jzfb.cfg & MODE_MASK) {
  373. + case MODE_STN_MONO_DUAL:
  374. + case MODE_STN_COLOR_DUAL:
  375. + case MODE_STN_MONO_SINGLE:
  376. + case MODE_STN_COLOR_SINGLE:
  377. + switch (jzfb.cfg & STN_DAT_PINMASK) {
  378. + case STN_DAT_PIN1:
  379. + /* Do not adjust the hori-param value. */
  380. + break;
  381. + case STN_DAT_PIN2:
  382. + align2(jzfb.hsw);
  383. + align2(jzfb.elw);
  384. + align2(jzfb.blw);
  385. + break;
  386. + case STN_DAT_PIN4:
  387. + align4(jzfb.hsw);
  388. + align4(jzfb.elw);
  389. + align4(jzfb.blw);
  390. + break;
  391. + case STN_DAT_PIN8:
  392. + align8(jzfb.hsw);
  393. + align8(jzfb.elw);
  394. + align8(jzfb.blw);
  395. + break;
  396. + }
  397. + break;
  398. + }
  399. +
  400. + REG_LCD_CTRL = val;
  401. +
  402. + switch (jzfb.cfg & MODE_MASK) {
  403. + case MODE_STN_MONO_DUAL:
  404. + case MODE_STN_COLOR_DUAL:
  405. + case MODE_STN_MONO_SINGLE:
  406. + case MODE_STN_COLOR_SINGLE:
  407. + if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
  408. + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
  409. + stnH = jzfb.h >> 1;
  410. + else
  411. + stnH = jzfb.h;
  412. +
  413. + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
  414. + REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
  415. +
  416. + /* Screen setting */
  417. + REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
  418. + REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
  419. + REG_LCD_DAV = (0 << 16) | (stnH);
  420. +
  421. + /* AC BIAs signal */
  422. + REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
  423. +
  424. + break;
  425. +
  426. + case MODE_TFT_GEN:
  427. + case MODE_TFT_SHARP:
  428. + case MODE_TFT_CASIO:
  429. + case MODE_TFT_SAMSUNG:
  430. + case MODE_8BIT_SERIAL_TFT:
  431. + case MODE_TFT_18BIT:
  432. + REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
  433. + REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
  434. + REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
  435. + REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
  436. + REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
  437. + | (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
  438. + break;
  439. + }
  440. +
  441. + switch (jzfb.cfg & MODE_MASK) {
  442. + case MODE_TFT_SAMSUNG:
  443. + {
  444. + unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
  445. + unsigned int rev_s, rev_e, inv_s, inv_e;
  446. +
  447. + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
  448. + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
  449. +
  450. + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
  451. + tp_s = jzfb.blw + jzfb.w + 1;
  452. + tp_e = tp_s + 1;
  453. + ckv_s = tp_s - pclk/(1000000000/4100);
  454. + ckv_e = tp_s + total;
  455. + rev_s = tp_s - 11; /* -11.5 clk */
  456. + rev_e = rev_s + total;
  457. + inv_s = tp_s;
  458. + inv_e = inv_s + total;
  459. + REG_LCD_CLS = (tp_s << 16) | tp_e;
  460. + REG_LCD_PS = (ckv_s << 16) | ckv_e;
  461. + REG_LCD_SPL = (rev_s << 16) | rev_e;
  462. + REG_LCD_REV = (inv_s << 16) | inv_e;
  463. + jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
  464. + break;
  465. + }
  466. + case MODE_TFT_SHARP:
  467. + {
  468. + unsigned int total, cls_s, cls_e, ps_s, ps_e;
  469. + unsigned int spl_s, spl_e, rev_s, rev_e;
  470. + total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
  471. + spl_s = 1;
  472. + spl_e = spl_s + 1;
  473. + cls_s = 0;
  474. + cls_e = total - 60; /* > 4us (pclk = 80ns) */
  475. + ps_s = cls_s;
  476. + ps_e = cls_e;
  477. + rev_s = total - 40; /* > 3us (pclk = 80ns) */
  478. + rev_e = rev_s + total;
  479. + jzfb.cfg |= STFT_PSHI;
  480. + REG_LCD_SPL = (spl_s << 16) | spl_e;
  481. + REG_LCD_CLS = (cls_s << 16) | cls_e;
  482. + REG_LCD_PS = (ps_s << 16) | ps_e;
  483. + REG_LCD_REV = (rev_s << 16) | rev_e;
  484. + break;
  485. + }
  486. + case MODE_TFT_CASIO:
  487. + break;
  488. + }
  489. +
  490. + /* Configure the LCD panel */
  491. + REG_LCD_CFG = jzfb.cfg;
  492. +
  493. + /* Timing setting */
  494. + __cpm_stop_lcd();
  495. +
  496. + val = jzfb.fclk; /* frame clk */
  497. + if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
  498. + pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
  499. + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
  500. + } else {
  501. + /* serial mode: Hsync period = 3*Width_Pixel */
  502. + pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
  503. + (jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
  504. + }
  505. +
  506. + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
  507. + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
  508. + pclk = (pclk * 3);
  509. +
  510. + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
  511. + ((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
  512. + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
  513. + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
  514. + pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
  515. +
  516. + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
  517. + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
  518. + pclk >>= 1;
  519. +
  520. + pll_div = (REG_CPM_CPCCR & CPM_CPCCR_PCS); /* clock source,0:pllout/2 1: pllout */
  521. + pll_div = pll_div ? 1 : 2;
  522. + val = (__cpm_get_pllout() / pll_div) / pclk;
  523. + val--;
  524. + if (val > 0x1ff) {
  525. + printf("CPM_LPCDR too large, set it to 0x1ff\n");
  526. + val = 0x1ff;
  527. + }
  528. + __cpm_set_pixdiv(val);
  529. +
  530. + val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
  531. + if (val > 150000000) {
  532. + printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
  533. + printf("Change LCDClock to 150MHz\n");
  534. + val = 150000000;
  535. + }
  536. + val = (__cpm_get_pllout() / pll_div) / val;
  537. + val--;
  538. + if (val > 0x1f) {
  539. + printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
  540. + val = 0x1f;
  541. + }
  542. + __cpm_set_ldiv( val );
  543. + REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
  544. +
  545. + __cpm_start_lcd();
  546. + udelay(1000);
  547. +
  548. + REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
  549. +
  550. + if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
  551. + ((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
  552. + REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
  553. +
  554. + return 0;
  555. +}
  556. +
  557. +void lcd_ctrl_init (void *lcdbase)
  558. +{
  559. + __lcd_display_pin_init();
  560. + __lcd_display_on() ;
  561. +
  562. + jz_lcd_init_mem(lcdbase, &panel_info);
  563. + jz_lcd_desc_init(&panel_info);
  564. + jz_lcd_hw_init(&panel_info);
  565. +
  566. +}
  567. +
  568. +/*
  569. + * Before enabled lcd controller, lcd registers should be configured correctly.
  570. + */
  571. +void lcd_enable (void)
  572. +{
  573. + REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
  574. + REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
  575. +}
  576. +
  577. +void lcd_disable (void)
  578. +{
  579. + REG_LCD_CTRL |= (1<<4);
  580. +}
  581. +
  582. +void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
  583. +{
  584. +}
  585. +
  586. +void lcd_initcolregs (void)
  587. +{
  588. +}
  589. diff --git a/drivers/video/nanonote_gpm940b0.h b/drivers/video/nanonote_gpm940b0.h
  590. new file mode 100644
  591. index 0000000..efe491e
  592. --- /dev/null
  593. +++ b/drivers/video/nanonote_gpm940b0.h
  594. @@ -0,0 +1,135 @@
  595. +/*
  596. + * JzRISC lcd controller
  597. + *
  598. + * Xiangfu Liu <xiangfu@sharism.cc>
  599. + *
  600. + * This program is free software; you can redistribute it and/or
  601. + * modify it under the terms of the GNU General Public License as
  602. + * published by the Free Software Foundation; either version 2 of
  603. + * the License, or (at your option) any later version.
  604. + *
  605. + * This program is distributed in the hope that it will be useful,
  606. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  607. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  608. + * GNU General Public License for more details.
  609. + *
  610. + * You should have received a copy of the GNU General Public License
  611. + * along with this program; if not, write to the Free Software
  612. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  613. + * MA 02111-1307 USA
  614. + */
  615. +
  616. +#ifndef __QI_LB60_GPM940B0_H__
  617. +#define __QI_LB60_GPM940B0_H__
  618. +
  619. +struct lcd_desc{
  620. + unsigned int next_desc; /* LCDDAx */
  621. + unsigned int databuf; /* LCDSAx */
  622. + unsigned int frame_id; /* LCDFIDx */
  623. + unsigned int cmd; /* LCDCMDx */
  624. +};
  625. +
  626. +#define MODE_MASK 0x0f
  627. +#define MODE_TFT_GEN 0x00
  628. +#define MODE_TFT_SHARP 0x01
  629. +#define MODE_TFT_CASIO 0x02
  630. +#define MODE_TFT_SAMSUNG 0x03
  631. +#define MODE_CCIR656_NONINT 0x04
  632. +#define MODE_CCIR656_INT 0x05
  633. +#define MODE_STN_COLOR_SINGLE 0x08
  634. +#define MODE_STN_MONO_SINGLE 0x09
  635. +#define MODE_STN_COLOR_DUAL 0x0a
  636. +#define MODE_STN_MONO_DUAL 0x0b
  637. +#define MODE_8BIT_SERIAL_TFT 0x0c
  638. +
  639. +#define MODE_TFT_18BIT (1<<7)
  640. +
  641. +#define STN_DAT_PIN1 (0x00 << 4)
  642. +#define STN_DAT_PIN2 (0x01 << 4)
  643. +#define STN_DAT_PIN4 (0x02 << 4)
  644. +#define STN_DAT_PIN8 (0x03 << 4)
  645. +#define STN_DAT_PINMASK STN_DAT_PIN8
  646. +
  647. +#define STFT_PSHI (1 << 15)
  648. +#define STFT_CLSHI (1 << 14)
  649. +#define STFT_SPLHI (1 << 13)
  650. +#define STFT_REVHI (1 << 12)
  651. +
  652. +#define SYNC_MASTER (0 << 16)
  653. +#define SYNC_SLAVE (1 << 16)
  654. +
  655. +#define DE_P (0 << 9)
  656. +#define DE_N (1 << 9)
  657. +
  658. +#define PCLK_P (0 << 10)
  659. +#define PCLK_N (1 << 10)
  660. +
  661. +#define HSYNC_P (0 << 11)
  662. +#define HSYNC_N (1 << 11)
  663. +
  664. +#define VSYNC_P (0 << 8)
  665. +#define VSYNC_N (1 << 8)
  666. +
  667. +#define DATA_NORMAL (0 << 17)
  668. +#define DATA_INVERSE (1 << 17)
  669. +
  670. +
  671. +/* Jz LCDFB supported I/O controls. */
  672. +#define FBIOSETBACKLIGHT 0x4688
  673. +#define FBIODISPON 0x4689
  674. +#define FBIODISPOFF 0x468a
  675. +#define FBIORESET 0x468b
  676. +#define FBIOPRINT_REG 0x468c
  677. +
  678. +/*
  679. + * LCD panel specific definition
  680. + */
  681. +#define MODE (0xc9) /* 8bit serial RGB */
  682. +
  683. +#define __spi_write_reg1(reg, val) \
  684. +do { \
  685. + unsigned char no; \
  686. + unsigned short value; \
  687. + unsigned char a=reg; \
  688. + unsigned char b=val; \
  689. + __gpio_set_pin(SPEN); \
  690. + __gpio_set_pin(SPCK); \
  691. + __gpio_clear_pin(SPDA); \
  692. + __gpio_clear_pin(SPEN); \
  693. + value=((a<<8)|(b&0xFF)); \
  694. + for(no=0;no<16;no++) \
  695. + { \
  696. + __gpio_clear_pin(SPCK); \
  697. + if((value&0x8000)==0x8000) \
  698. + __gpio_set_pin(SPDA); \
  699. + else \
  700. + __gpio_clear_pin(SPDA); \
  701. + __gpio_set_pin(SPCK); \
  702. + value=(value<<1); \
  703. + } \
  704. + __gpio_set_pin(SPEN); \
  705. +} while (0)
  706. +
  707. +#define __lcd_display_pin_init() \
  708. +do { \
  709. + __cpm_start_tcu(); \
  710. + __gpio_as_output(SPEN); /* use SPDA */ \
  711. + __gpio_as_output(SPCK); /* use SPCK */ \
  712. + __gpio_as_output(SPDA); /* use SPDA */ \
  713. +} while (0)
  714. +
  715. +#define __lcd_display_on() \
  716. +do { \
  717. + __spi_write_reg1(0x05, 0x1e); \
  718. + __spi_write_reg1(0x05, 0x5e); \
  719. + __spi_write_reg1(0x07, 0x8d); \
  720. + __spi_write_reg1(0x13, 0x01); \
  721. + __spi_write_reg1(0x05, 0x5f); \
  722. +} while (0)
  723. +
  724. +#define __lcd_display_off() \
  725. +do { \
  726. + __spi_write_reg1(0x05, 0x5e); \
  727. +} while (0)
  728. +
  729. +#endif /* __QI_LB60_GPM940B0_H__ */
  730. diff --git a/include/configs/qi_lb60.h b/include/configs/qi_lb60.h
  731. index 52b370c..d3e78ad 100644
  732. --- a/include/configs/qi_lb60.h
  733. +++ b/include/configs/qi_lb60.h
  734. @@ -32,6 +32,13 @@
  735. * Miscellaneous configurable options
  736. */
  737. #define CONFIG_NANONOTE
  738. +
  739. +#define CONFIG_LCD
  740. +#define CONFIG_SYS_WHITE_ON_BLACK
  741. +#define LCD_BPP LCD_COLOR32
  742. +#define CONFIG_VIDEO_GPM940B0
  743. +
  744. +
  745. #define CONFIG_JZ4740_MMC
  746. #define CONFIG_MMC 1
  747. #define CONFIG_FAT 1
  748. diff --git a/include/lcd.h b/include/lcd.h
  749. index 42070d7..6de5482 100644
  750. --- a/include/lcd.h
  751. +++ b/include/lcd.h
  752. @@ -263,8 +263,44 @@ typedef struct vidinfo {
  753. void init_panel_info(vidinfo_t *vid);
  754. -#else
  755. +#elif defined(CONFIG_JZSOC)
  756. +/*
  757. + * LCD controller stucture for JZSOC: JZ4740
  758. + */
  759. +struct jz_fb_dma_descriptor {
  760. + u_long fdadr; /* Frame descriptor address register */
  761. + u_long fsadr; /* Frame source address register */
  762. + u_long fidr; /* Frame ID register */
  763. + u_long ldcmd; /* Command register */
  764. +};
  765. +
  766. +/*
  767. + * Jz LCD info
  768. + */
  769. +struct jz_fb_info {
  770. +
  771. + u_long fdadr0; /* physical address of frame/palette descriptor */
  772. + u_long fdadr1; /* physical address of frame descriptor */
  773. +
  774. + /* DMA descriptors */
  775. + struct jz_fb_dma_descriptor * dmadesc_fblow;
  776. + struct jz_fb_dma_descriptor * dmadesc_fbhigh;
  777. + struct jz_fb_dma_descriptor * dmadesc_palette;
  778. + u_long screen; /* address of frame buffer */
  779. + u_long palette; /* address of palette memory */
  780. + u_int palette_size;
  781. +};
  782. +typedef struct vidinfo {
  783. + ushort vl_col; /* Number of columns (i.e. 640) */
  784. + ushort vl_row; /* Number of rows (i.e. 480) */
  785. + u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
  786. +
  787. + struct jz_fb_info jz_fb;
  788. +} vidinfo_t;
  789. +
  790. +extern vidinfo_t panel_info;
  791. +#else
  792. typedef struct vidinfo {
  793. ushort vl_col; /* Number of columns (i.e. 160) */
  794. ushort vl_row; /* Number of rows (i.e. 100) */
  795. @@ -318,6 +354,7 @@ void lcd_show_board_info(void);
  796. #define LCD_COLOR4 2
  797. #define LCD_COLOR8 3
  798. #define LCD_COLOR16 4
  799. +#define LCD_COLOR32 5
  800. /*----------------------------------------------------------------------*/
  801. #if defined(CONFIG_LCD_INFO_BELOW_LOGO)
  802. @@ -369,7 +406,7 @@ void lcd_show_board_info(void);
  803. # define CONSOLE_COLOR_GREY 14
  804. # define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
  805. -#else
  806. +#elif LCD_BPP == LCD_COLOR16
  807. /*
  808. * 16bpp color definitions
  809. @@ -377,6 +414,15 @@ void lcd_show_board_info(void);
  810. # define CONSOLE_COLOR_BLACK 0x0000
  811. # define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
  812. +#elif LCD_BPP == LCD_COLOR32
  813. +/*
  814. + * 18,24,32 bpp color definitions
  815. + */
  816. +# define CONSOLE_COLOR_BLACK 0x00000000
  817. +# define CONSOLE_COLOR_WHITE 0xffffffff /* Must remain last / highest */
  818. +
  819. +#else
  820. +
  821. #endif /* color definitions */
  822. /************************************************************************/
  823. @@ -406,7 +452,7 @@ void lcd_show_board_info(void);
  824. #if LCD_BPP == LCD_MONOCHROME
  825. # define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \
  826. (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
  827. -#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
  828. +#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || (LCD_BPP == LCD_COLOR32)
  829. # define COLOR_MASK(c) (c)
  830. #else
  831. # error Unsupported LCD BPP.
  832. --
  833. 1.7.9.5