600-0012-rt2x00-rt2800lib-add-channel-configuration-function-.patch 6.1 KB

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  1. From 6e3a17190815c6aa4dc53c2cfe9125fb1154f187 Mon Sep 17 00:00:00 2001
  2. From: Gabor Juhos <juhosg@openwrt.org>
  3. Date: Sun, 24 Mar 2013 19:26:27 +0100
  4. Subject: [PATCH] rt2x00: rt2800lib: add channel configuration function for
  5. RF3853
  6. Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  7. ---
  8. drivers/net/wireless/rt2x00/rt2800lib.c | 208 +++++++++++++++++++++++++++++++
  9. 1 file changed, 208 insertions(+)
  10. --- a/drivers/net/wireless/rt2x00/rt2800lib.c
  11. +++ b/drivers/net/wireless/rt2x00/rt2800lib.c
  12. @@ -2649,6 +2649,211 @@ static void rt2800_config_channel_rf3053
  13. }
  14. }
  15. +static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
  16. + struct ieee80211_conf *conf,
  17. + struct rf_channel *rf,
  18. + struct channel_info *info)
  19. +{
  20. + u8 rfcsr;
  21. + u8 bbp;
  22. + u8 pwr1, pwr2, pwr3;
  23. +
  24. + const bool txbf_enabled = false; /* TODO */
  25. +
  26. + /* TODO: add band selection */
  27. +
  28. + if (rf->channel <= 14)
  29. + rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
  30. + else if (rf->channel < 132)
  31. + rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
  32. + else
  33. + rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
  34. +
  35. + rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
  36. + rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
  37. +
  38. + if (rf->channel <= 14)
  39. + rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
  40. + else
  41. + rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
  42. +
  43. + if (rf->channel <= 14)
  44. + rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
  45. + else
  46. + rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
  47. +
  48. + rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
  49. +
  50. + rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  51. + rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
  52. + rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
  53. + rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
  54. + rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
  55. + rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
  56. + rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
  57. + rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
  58. + rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
  59. +
  60. + switch (rt2x00dev->default_ant.tx_chain_num) {
  61. + case 3:
  62. + rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
  63. + /* fallthrough */
  64. + case 2:
  65. + rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
  66. + /* fallthrough */
  67. + case 1:
  68. + rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
  69. + break;
  70. + }
  71. +
  72. + switch (rt2x00dev->default_ant.rx_chain_num) {
  73. + case 3:
  74. + rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
  75. + /* fallthrough */
  76. + case 2:
  77. + rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
  78. + /* fallthrough */
  79. + case 1:
  80. + rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
  81. + break;
  82. + }
  83. + rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  84. +
  85. + rt2800_adjust_freq_offset(rt2x00dev);
  86. +
  87. + rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
  88. + if (!conf_is_ht40(conf))
  89. + rfcsr &= ~(0x06);
  90. + else
  91. + rfcsr |= 0x06;
  92. + rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  93. +
  94. + if (rf->channel <= 14)
  95. + rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
  96. + else
  97. + rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
  98. +
  99. + if (conf_is_ht40(conf))
  100. + rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
  101. + else
  102. + rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
  103. +
  104. + if (rf->channel <= 14)
  105. + rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
  106. + else
  107. + rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
  108. +
  109. + /* loopback RF_BS */
  110. + rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
  111. + if (rf->channel <= 14)
  112. + rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
  113. + else
  114. + rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
  115. + rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
  116. +
  117. + if (rf->channel <= 14)
  118. + rfcsr = 0x23;
  119. + else if (rf->channel < 100)
  120. + rfcsr = 0x36;
  121. + else if (rf->channel < 132)
  122. + rfcsr = 0x32;
  123. + else
  124. + rfcsr = 0x30;
  125. +
  126. + if (txbf_enabled)
  127. + rfcsr |= 0x40;
  128. +
  129. + rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
  130. +
  131. + if (rf->channel <= 14)
  132. + rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
  133. + else
  134. + rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
  135. +
  136. + if (rf->channel <= 14)
  137. + rfcsr = 0xbb;
  138. + else if (rf->channel < 100)
  139. + rfcsr = 0xeb;
  140. + else if (rf->channel < 132)
  141. + rfcsr = 0xb3;
  142. + else
  143. + rfcsr = 0x9b;
  144. + rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
  145. +
  146. + if (rf->channel <= 14)
  147. + rfcsr = 0x8e;
  148. + else
  149. + rfcsr = 0x8a;
  150. +
  151. + if (txbf_enabled)
  152. + rfcsr |= 0x20;
  153. +
  154. + rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
  155. +
  156. + rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
  157. +
  158. + rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
  159. + if (rf->channel <= 14)
  160. + rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
  161. + else
  162. + rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
  163. +
  164. + rt2800_rfcsr_read(rt2x00dev, 52, &rfcsr);
  165. + if (rf->channel <= 14)
  166. + rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
  167. + else
  168. + rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
  169. +
  170. + if (rf->channel <= 14) {
  171. + pwr1 = info->default_power1 & 0x1f;
  172. + pwr2 = info->default_power2 & 0x1f;
  173. + pwr3 = info->default_power3 & 0x1f;
  174. + } else {
  175. + pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) |
  176. + (info->default_power1 & 0x7);
  177. + pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) |
  178. + (info->default_power2 & 0x7);
  179. + pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) |
  180. + (info->default_power3 & 0x7);
  181. + }
  182. +
  183. + rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
  184. + rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
  185. + rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
  186. +
  187. + rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
  188. + rf->channel, pwr1, pwr2, pwr3);
  189. +
  190. + bbp = (info->default_power1 >> 5) |
  191. + ((info->default_power2 & 0xe0) >> 1);
  192. + rt2800_bbp_write(rt2x00dev, 109, bbp);
  193. +
  194. + rt2800_bbp_read(rt2x00dev, 110, &bbp);
  195. + bbp &= 0x0f;
  196. + bbp |= (info->default_power3 & 0xe0) >> 1;
  197. + rt2800_bbp_write(rt2x00dev, 110, bbp);
  198. +
  199. + rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
  200. + if (rf->channel <= 14)
  201. + rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
  202. + else
  203. + rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
  204. +
  205. + /* Enable RF tuning */
  206. + rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
  207. + rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
  208. + rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
  209. +
  210. + udelay(2000);
  211. +
  212. + rt2800_bbp_read(rt2x00dev, 49, &bbp);
  213. + /* clear update flag */
  214. + rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
  215. + rt2800_bbp_write(rt2x00dev, 49, bbp);
  216. +
  217. + /* TODO: add calibration for TxBF */
  218. +}
  219. +
  220. #define POWER_BOUND 0x27
  221. #define POWER_BOUND_5G 0x2b
  222. @@ -3261,6 +3466,9 @@ static void rt2800_config_channel(struct
  223. case RF3322:
  224. rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
  225. break;
  226. + case RF3853:
  227. + rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
  228. + break;
  229. case RF3070:
  230. case RF5360:
  231. case RF5362: