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- From 35b7dfc295f4d6079572a22a225c7444134e1f72 Mon Sep 17 00:00:00 2001
- From: Chen-Yu Tsai <wens@csie.org>
- Date: Mon, 3 Feb 2014 09:51:41 +0800
- Subject: [PATCH] ARM: dts: sun4i: rename clock node names to clk@N
- Device tree naming conventions state that node names should match
- node function. Change fully functioning clock nodes to match and
- add clock-output-names to all sunxi clock nodes.
- Signed-off-by: Chen-Yu Tsai <wens@csie.org>
- Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
- ---
- arch/arm/boot/dts/sun4i-a10.dtsi | 30 ++++++++++++++++++++----------
- 1 file changed, 20 insertions(+), 10 deletions(-)
- --- a/arch/arm/boot/dts/sun4i-a10.dtsi
- +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
- @@ -58,34 +58,38 @@
- clock-frequency = <0>;
- };
-
- - osc24M: osc24M@01c20050 {
- + osc24M: clk@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-osc-clk";
- reg = <0x01c20050 0x4>;
- clock-frequency = <24000000>;
- + clock-output-names = "osc24M";
- };
-
- - osc32k: osc32k {
- + osc32k: clk@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- + clock-output-names = "osc32k";
- };
-
- - pll1: pll1@01c20000 {
- + pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
- + clock-output-names = "pll1";
- };
-
- - pll4: pll4@01c20018 {
- + pll4: clk@01c20018 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-pll1-clk";
- reg = <0x01c20018 0x4>;
- clocks = <&osc24M>;
- + clock-output-names = "pll4";
- };
-
- - pll5: pll5@01c20020 {
- + pll5: clk@01c20020 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll5-clk";
- reg = <0x01c20020 0x4>;
- @@ -93,7 +97,7 @@
- clock-output-names = "pll5_ddr", "pll5_other";
- };
-
- - pll6: pll6@01c20028 {
- + pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-pll6-clk";
- reg = <0x01c20028 0x4>;
- @@ -107,6 +111,7 @@
- compatible = "allwinner,sun4i-cpu-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
- + clock-output-names = "cpu";
- };
-
- axi: axi@01c20054 {
- @@ -114,9 +119,10 @@
- compatible = "allwinner,sun4i-axi-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&cpu>;
- + clock-output-names = "axi";
- };
-
- - axi_gates: axi_gates@01c2005c {
- + axi_gates: clk@01c2005c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-axi-gates-clk";
- reg = <0x01c2005c 0x4>;
- @@ -129,9 +135,10 @@
- compatible = "allwinner,sun4i-ahb-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&axi>;
- + clock-output-names = "ahb";
- };
-
- - ahb_gates: ahb_gates@01c20060 {
- + ahb_gates: clk@01c20060 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-ahb-gates-clk";
- reg = <0x01c20060 0x8>;
- @@ -154,9 +161,10 @@
- compatible = "allwinner,sun4i-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb>;
- + clock-output-names = "apb0";
- };
-
- - apb0_gates: apb0_gates@01c20068 {
- + apb0_gates: clk@01c20068 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-apb0-gates-clk";
- reg = <0x01c20068 0x4>;
- @@ -171,6 +179,7 @@
- compatible = "allwinner,sun4i-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- + clock-output-names = "apb1_mux";
- };
-
- apb1: apb1@01c20058 {
- @@ -178,9 +187,10 @@
- compatible = "allwinner,sun4i-apb1-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&apb1_mux>;
- + clock-output-names = "apb1";
- };
-
- - apb1_gates: apb1_gates@01c2006c {
- + apb1_gates: clk@01c2006c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-apb1-gates-clk";
- reg = <0x01c2006c 0x4>;
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