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140-dt-sunxi-convert-to-new-clock-compats.patch

140-dt-sunxi-convert-to-new-clock-compats.patch 30 KB
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  1. From 46b2ee17d7321149b4d48dd86ee2e346624aa141 Mon Sep 17 00:00:00 2001
    2. 

  2. From: Maxime Ripard <maxime.ripard@free-electrons.com>
    3. 

  3. Date: Thu, 6 Feb 2014 09:55:58 +0100
    4. 

  4. Subject: [PATCH] ARM: sunxi: dt: Convert to the new clock compatibles
    5. 

  5. 

  6. Switch the device tree to the new compatibles introduced in the clock drivers
    7. 

  7. to have a common pattern accross all Allwinner SoCs.
    8. 

  8. 

  9. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
    10. 

  10. ---
    11. 

  11.  arch/arm/boot/dts/sun4i-a10.dtsi  | 60 +++++++++++++++++++--------------------
    12. 

  12.  arch/arm/boot/dts/sun5i-a10s.dtsi | 48 +++++++++++++++----------------
    13. 

  13.  arch/arm/boot/dts/sun5i-a13.dtsi  | 48 +++++++++++++++----------------
    14. 

  14.  arch/arm/boot/dts/sun6i-a31.dtsi  | 10 +++----
    15. 

  15.  arch/arm/boot/dts/sun7i-a20.dtsi  | 54 +++++++++++++++++------------------
    16. 

  16.  5 files changed, 110 insertions(+), 110 deletions(-)
    17. 

  17. 

  18. --- a/arch/arm/boot/dts/sun4i-a10.dtsi
    19. 

  19. +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
    20. 

  20. @@ -60,7 +60,7 @@
    21. 

  21.  
    22. 

  22.  		osc24M: clk@01c20050 {
    23. 

  23.  			#clock-cells = <0>;
    24. 

  24. -			compatible = "allwinner,sun4i-osc-clk";
    25. 

  25. +			compatible = "allwinner,sun4i-a10-osc-clk";
    26. 

  26.  			reg = <0x01c20050 0x4>;
    27. 

  27.  			clock-frequency = <24000000>;
    28. 

  28.  			clock-output-names = "osc24M";
    29. 

  29. @@ -75,7 +75,7 @@
    30. 

  30.  
    31. 

  31.  		pll1: clk@01c20000 {
    32. 

  32.  			#clock-cells = <0>;
    33. 

  33. -			compatible = "allwinner,sun4i-pll1-clk";
    34. 

  34. +			compatible = "allwinner,sun4i-a10-pll1-clk";
    35. 

  35.  			reg = <0x01c20000 0x4>;
    36. 

  36.  			clocks = <&osc24M>;
    37. 

  37.  			clock-output-names = "pll1";
    38. 

  38. @@ -83,7 +83,7 @@
    39. 

  39.  
    40. 

  40.  		pll4: clk@01c20018 {
    41. 

  41.  			#clock-cells = <0>;
    42. 

  42. -			compatible = "allwinner,sun4i-pll1-clk";
    43. 

  43. +			compatible = "allwinner,sun4i-a10-pll1-clk";
    44. 

  44.  			reg = <0x01c20018 0x4>;
    45. 

  45.  			clocks = <&osc24M>;
    46. 

  46.  			clock-output-names = "pll4";
    47. 

  47. @@ -91,7 +91,7 @@
    48. 

  48.  
    49. 

  49.  		pll5: clk@01c20020 {
    50. 

  50.  			#clock-cells = <1>;
    51. 

  51. -			compatible = "allwinner,sun4i-pll5-clk";
    52. 

  52. +			compatible = "allwinner,sun4i-a10-pll5-clk";
    53. 

  53.  			reg = <0x01c20020 0x4>;
    54. 

  54.  			clocks = <&osc24M>;
    55. 

  55.  			clock-output-names = "pll5_ddr", "pll5_other";
    56. 

  56. @@ -99,7 +99,7 @@
    57. 

  57.  
    58. 

  58.  		pll6: clk@01c20028 {
    59. 

  59.  			#clock-cells = <1>;
    60. 

  60. -			compatible = "allwinner,sun4i-pll6-clk";
    61. 

  61. +			compatible = "allwinner,sun4i-a10-pll6-clk";
    62. 

  62.  			reg = <0x01c20028 0x4>;
    63. 

  63.  			clocks = <&osc24M>;
    64. 

  64.  			clock-output-names = "pll6_sata", "pll6_other", "pll6";
    65. 

  65. @@ -108,7 +108,7 @@
    66. 

  66.  		/* dummy is 200M */
    67. 

  67.  		cpu: cpu@01c20054 {
    68. 

  68.  			#clock-cells = <0>;
    69. 

  69. -			compatible = "allwinner,sun4i-cpu-clk";
    70. 

  70. +			compatible = "allwinner,sun4i-a10-cpu-clk";
    71. 

  71.  			reg = <0x01c20054 0x4>;
    72. 

  72.  			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
    73. 

  73.  			clock-output-names = "cpu";
    74. 

  74. @@ -116,7 +116,7 @@
    75. 

  75.  
    76. 

  76.  		axi: axi@01c20054 {
    77. 

  77.  			#clock-cells = <0>;
    78. 

  78. -			compatible = "allwinner,sun4i-axi-clk";
    79. 

  79. +			compatible = "allwinner,sun4i-a10-axi-clk";
    80. 

  80.  			reg = <0x01c20054 0x4>;
    81. 

  81.  			clocks = <&cpu>;
    82. 

  82.  			clock-output-names = "axi";
    83. 

  83. @@ -124,7 +124,7 @@
    84. 

  84.  
    85. 

  85.  		axi_gates: clk@01c2005c {
    86. 

  86.  			#clock-cells = <1>;
    87. 

  87. -			compatible = "allwinner,sun4i-axi-gates-clk";
    88. 

  88. +			compatible = "allwinner,sun4i-a10-axi-gates-clk";
    89. 

  89.  			reg = <0x01c2005c 0x4>;
    90. 

  90.  			clocks = <&axi>;
    91. 

  91.  			clock-output-names = "axi_dram";
    92. 

  92. @@ -132,7 +132,7 @@
    93. 

  93.  
    94. 

  94.  		ahb: ahb@01c20054 {
    95. 

  95.  			#clock-cells = <0>;
    96. 

  96. -			compatible = "allwinner,sun4i-ahb-clk";
    97. 

  97. +			compatible = "allwinner,sun4i-a10-ahb-clk";
    98. 

  98.  			reg = <0x01c20054 0x4>;
    99. 

  99.  			clocks = <&axi>;
    100. 

  100.  			clock-output-names = "ahb";
    101. 

  101. @@ -140,7 +140,7 @@
    102. 

  102.  
    103. 

  103.  		ahb_gates: clk@01c20060 {
    104. 

  104.  			#clock-cells = <1>;
    105. 

  105. -			compatible = "allwinner,sun4i-ahb-gates-clk";
    106. 

  106. +			compatible = "allwinner,sun4i-a10-ahb-gates-clk";
    107. 

  107.  			reg = <0x01c20060 0x8>;
    108. 

  108.  			clocks = <&ahb>;
    109. 

  109.  			clock-output-names = "ahb_usb0", "ahb_ehci0",
    110. 

  110. @@ -158,7 +158,7 @@
    111. 

  111.  
    112. 

  112.  		apb0: apb0@01c20054 {
    113. 

  113.  			#clock-cells = <0>;
    114. 

  114. -			compatible = "allwinner,sun4i-apb0-clk";
    115. 

  115. +			compatible = "allwinner,sun4i-a10-apb0-clk";
    116. 

  116.  			reg = <0x01c20054 0x4>;
    117. 

  117.  			clocks = <&ahb>;
    118. 

  118.  			clock-output-names = "apb0";
    119. 

  119. @@ -166,7 +166,7 @@
    120. 

  120.  
    121. 

  121.  		apb0_gates: clk@01c20068 {
    122. 

  122.  			#clock-cells = <1>;
    123. 

  123. -			compatible = "allwinner,sun4i-apb0-gates-clk";
    124. 

  124. +			compatible = "allwinner,sun4i-a10-apb0-gates-clk";
    125. 

  125.  			reg = <0x01c20068 0x4>;
    126. 

  126.  			clocks = <&apb0>;
    127. 

  127.  			clock-output-names = "apb0_codec", "apb0_spdif",
    128. 

  128. @@ -176,7 +176,7 @@
    129. 

  129.  
    130. 

  130.  		apb1_mux: apb1_mux@01c20058 {
    131. 

  131.  			#clock-cells = <0>;
    132. 

  132. -			compatible = "allwinner,sun4i-apb1-mux-clk";
    133. 

  133. +			compatible = "allwinner,sun4i-a10-apb1-mux-clk";
    134. 

  134.  			reg = <0x01c20058 0x4>;
    135. 

  135.  			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
    136. 

  136.  			clock-output-names = "apb1_mux";
    137. 

  137. @@ -184,7 +184,7 @@
    138. 

  138.  
    139. 

  139.  		apb1: apb1@01c20058 {
    140. 

  140.  			#clock-cells = <0>;
    141. 

  141. -			compatible = "allwinner,sun4i-apb1-clk";
    142. 

  142. +			compatible = "allwinner,sun4i-a10-apb1-clk";
    143. 

  143.  			reg = <0x01c20058 0x4>;
    144. 

  144.  			clocks = <&apb1_mux>;
    145. 

  145.  			clock-output-names = "apb1";
    146. 

  146. @@ -192,7 +192,7 @@
    147. 

  147.  
    148. 

  148.  		apb1_gates: clk@01c2006c {
    149. 

  149.  			#clock-cells = <1>;
    150. 

  150. -			compatible = "allwinner,sun4i-apb1-gates-clk";
    151. 

  151. +			compatible = "allwinner,sun4i-a10-apb1-gates-clk";
    152. 

  152.  			reg = <0x01c2006c 0x4>;
    153. 

  153.  			clocks = <&apb1>;
    154. 

  154.  			clock-output-names = "apb1_i2c0", "apb1_i2c1",
    155. 

  155. @@ -205,7 +205,7 @@
    156. 

  156.  
    157. 

  157.  		nand_clk: clk@01c20080 {
    158. 

  158.  			#clock-cells = <0>;
    159. 

  159. -			compatible = "allwinner,sun4i-mod0-clk";
    160. 

  160. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    161. 

  161.  			reg = <0x01c20080 0x4>;
    162. 

  162.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    163. 

  163.  			clock-output-names = "nand";
    164. 

  164. @@ -213,7 +213,7 @@
    165. 

  165.  
    166. 

  166.  		ms_clk: clk@01c20084 {
    167. 

  167.  			#clock-cells = <0>;
    168. 

  168. -			compatible = "allwinner,sun4i-mod0-clk";
    169. 

  169. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    170. 

  170.  			reg = <0x01c20084 0x4>;
    171. 

  171.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    172. 

  172.  			clock-output-names = "ms";
    173. 

  173. @@ -221,7 +221,7 @@
    174. 

  174.  
    175. 

  175.  		mmc0_clk: clk@01c20088 {
    176. 

  176.  			#clock-cells = <0>;
    177. 

  177. -			compatible = "allwinner,sun4i-mod0-clk";
    178. 

  178. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    179. 

  179.  			reg = <0x01c20088 0x4>;
    180. 

  180.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    181. 

  181.  			clock-output-names = "mmc0";
    182. 

  182. @@ -229,7 +229,7 @@
    183. 

  183.  
    184. 

  184.  		mmc1_clk: clk@01c2008c {
    185. 

  185.  			#clock-cells = <0>;
    186. 

  186. -			compatible = "allwinner,sun4i-mod0-clk";
    187. 

  187. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    188. 

  188.  			reg = <0x01c2008c 0x4>;
    189. 

  189.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    190. 

  190.  			clock-output-names = "mmc1";
    191. 

  191. @@ -237,7 +237,7 @@
    192. 

  192.  
    193. 

  193.  		mmc2_clk: clk@01c20090 {
    194. 

  194.  			#clock-cells = <0>;
    195. 

  195. -			compatible = "allwinner,sun4i-mod0-clk";
    196. 

  196. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    197. 

  197.  			reg = <0x01c20090 0x4>;
    198. 

  198.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    199. 

  199.  			clock-output-names = "mmc2";
    200. 

  200. @@ -245,7 +245,7 @@
    201. 

  201.  
    202. 

  202.  		mmc3_clk: clk@01c20094 {
    203. 

  203.  			#clock-cells = <0>;
    204. 

  204. -			compatible = "allwinner,sun4i-mod0-clk";
    205. 

  205. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    206. 

  206.  			reg = <0x01c20094 0x4>;
    207. 

  207.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    208. 

  208.  			clock-output-names = "mmc3";
    209. 

  209. @@ -253,7 +253,7 @@
    210. 

  210.  
    211. 

  211.  		ts_clk: clk@01c20098 {
    212. 

  212.  			#clock-cells = <0>;
    213. 

  213. -			compatible = "allwinner,sun4i-mod0-clk";
    214. 

  214. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    215. 

  215.  			reg = <0x01c20098 0x4>;
    216. 

  216.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    217. 

  217.  			clock-output-names = "ts";
    218. 

  218. @@ -261,7 +261,7 @@
    219. 

  219.  
    220. 

  220.  		ss_clk: clk@01c2009c {
    221. 

  221.  			#clock-cells = <0>;
    222. 

  222. -			compatible = "allwinner,sun4i-mod0-clk";
    223. 

  223. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    224. 

  224.  			reg = <0x01c2009c 0x4>;
    225. 

  225.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    226. 

  226.  			clock-output-names = "ss";
    227. 

  227. @@ -269,7 +269,7 @@
    228. 

  228.  
    229. 

  229.  		spi0_clk: clk@01c200a0 {
    230. 

  230.  			#clock-cells = <0>;
    231. 

  231. -			compatible = "allwinner,sun4i-mod0-clk";
    232. 

  232. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    233. 

  233.  			reg = <0x01c200a0 0x4>;
    234. 

  234.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    235. 

  235.  			clock-output-names = "spi0";
    236. 

  236. @@ -277,7 +277,7 @@
    237. 

  237.  
    238. 

  238.  		spi1_clk: clk@01c200a4 {
    239. 

  239.  			#clock-cells = <0>;
    240. 

  240. -			compatible = "allwinner,sun4i-mod0-clk";
    241. 

  241. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    242. 

  242.  			reg = <0x01c200a4 0x4>;
    243. 

  243.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    244. 

  244.  			clock-output-names = "spi1";
    245. 

  245. @@ -285,7 +285,7 @@
    246. 

  246.  
    247. 

  247.  		spi2_clk: clk@01c200a8 {
    248. 

  248.  			#clock-cells = <0>;
    249. 

  249. -			compatible = "allwinner,sun4i-mod0-clk";
    250. 

  250. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    251. 

  251.  			reg = <0x01c200a8 0x4>;
    252. 

  252.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    253. 

  253.  			clock-output-names = "spi2";
    254. 

  254. @@ -293,7 +293,7 @@
    255. 

  255.  
    256. 

  256.  		pata_clk: clk@01c200ac {
    257. 

  257.  			#clock-cells = <0>;
    258. 

  258. -			compatible = "allwinner,sun4i-mod0-clk";
    259. 

  259. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    260. 

  260.  			reg = <0x01c200ac 0x4>;
    261. 

  261.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    262. 

  262.  			clock-output-names = "pata";
    263. 

  263. @@ -301,7 +301,7 @@
    264. 

  264.  
    265. 

  265.  		ir0_clk: clk@01c200b0 {
    266. 

  266.  			#clock-cells = <0>;
    267. 

  267. -			compatible = "allwinner,sun4i-mod0-clk";
    268. 

  268. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    269. 

  269.  			reg = <0x01c200b0 0x4>;
    270. 

  270.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    271. 

  271.  			clock-output-names = "ir0";
    272. 

  272. @@ -309,7 +309,7 @@
    273. 

  273.  
    274. 

  274.  		ir1_clk: clk@01c200b4 {
    275. 

  275.  			#clock-cells = <0>;
    276. 

  276. -			compatible = "allwinner,sun4i-mod0-clk";
    277. 

  277. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    278. 

  278.  			reg = <0x01c200b4 0x4>;
    279. 

  279.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    280. 

  280.  			clock-output-names = "ir1";
    281. 

  281. @@ -326,7 +326,7 @@
    282. 

  282.  
    283. 

  283.  		spi3_clk: clk@01c200d4 {
    284. 

  284.  			#clock-cells = <0>;
    285. 

  285. -			compatible = "allwinner,sun4i-mod0-clk";
    286. 

  286. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    287. 

  287.  			reg = <0x01c200d4 0x4>;
    288. 

  288.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    289. 

  289.  			clock-output-names = "spi3";
    290. 

  290. --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
    291. 

  291. +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
    292. 

  292. @@ -49,7 +49,7 @@
    293. 

  293.  
    294. 

  294.  		osc24M: clk@01c20050 {
    295. 

  295.  			#clock-cells = <0>;
    296. 

  296. -			compatible = "allwinner,sun4i-osc-clk";
    297. 

  297. +			compatible = "allwinner,sun4i-a10-osc-clk";
    298. 

  298.  			reg = <0x01c20050 0x4>;
    299. 

  299.  			clock-frequency = <24000000>;
    300. 

  300.  			clock-output-names = "osc24M";
    301. 

  301. @@ -64,7 +64,7 @@
    302. 

  302.  
    303. 

  303.  		pll1: clk@01c20000 {
    304. 

  304.  			#clock-cells = <0>;
    305. 

  305. -			compatible = "allwinner,sun4i-pll1-clk";
    306. 

  306. +			compatible = "allwinner,sun4i-a10-pll1-clk";
    307. 

  307.  			reg = <0x01c20000 0x4>;
    308. 

  308.  			clocks = <&osc24M>;
    309. 

  309.  			clock-output-names = "pll1";
    310. 

  310. @@ -72,7 +72,7 @@
    311. 

  311.  
    312. 

  312.  		pll4: clk@01c20018 {
    313. 

  313.  			#clock-cells = <0>;
    314. 

  314. -			compatible = "allwinner,sun4i-pll1-clk";
    315. 

  315. +			compatible = "allwinner,sun4i-a10-pll1-clk";
    316. 

  316.  			reg = <0x01c20018 0x4>;
    317. 

  317.  			clocks = <&osc24M>;
    318. 

  318.  			clock-output-names = "pll4";
    319. 

  319. @@ -80,7 +80,7 @@
    320. 

  320.  
    321. 

  321.  		pll5: clk@01c20020 {
    322. 

  322.  			#clock-cells = <1>;
    323. 

  323. -			compatible = "allwinner,sun4i-pll5-clk";
    324. 

  324. +			compatible = "allwinner,sun4i-a10-pll5-clk";
    325. 

  325.  			reg = <0x01c20020 0x4>;
    326. 

  326.  			clocks = <&osc24M>;
    327. 

  327.  			clock-output-names = "pll5_ddr", "pll5_other";
    328. 

  328. @@ -88,7 +88,7 @@
    329. 

  329.  
    330. 

  330.  		pll6: clk@01c20028 {
    331. 

  331.  			#clock-cells = <1>;
    332. 

  332. -			compatible = "allwinner,sun4i-pll6-clk";
    333. 

  333. +			compatible = "allwinner,sun4i-a10-pll6-clk";
    334. 

  334.  			reg = <0x01c20028 0x4>;
    335. 

  335.  			clocks = <&osc24M>;
    336. 

  336.  			clock-output-names = "pll6_sata", "pll6_other", "pll6";
    337. 

  337. @@ -97,7 +97,7 @@
    338. 

  338.  		/* dummy is 200M */
    339. 

  339.  		cpu: cpu@01c20054 {
    340. 

  340.  			#clock-cells = <0>;
    341. 

  341. -			compatible = "allwinner,sun4i-cpu-clk";
    342. 

  342. +			compatible = "allwinner,sun4i-a10-cpu-clk";
    343. 

  343.  			reg = <0x01c20054 0x4>;
    344. 

  344.  			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
    345. 

  345.  			clock-output-names = "cpu";
    346. 

  346. @@ -105,7 +105,7 @@
    347. 

  347.  
    348. 

  348.  		axi: axi@01c20054 {
    349. 

  349.  			#clock-cells = <0>;
    350. 

  350. -			compatible = "allwinner,sun4i-axi-clk";
    351. 

  351. +			compatible = "allwinner,sun4i-a10-axi-clk";
    352. 

  352.  			reg = <0x01c20054 0x4>;
    353. 

  353.  			clocks = <&cpu>;
    354. 

  354.  			clock-output-names = "axi";
    355. 

  355. @@ -113,7 +113,7 @@
    356. 

  356.  
    357. 

  357.  		axi_gates: clk@01c2005c {
    358. 

  358.  			#clock-cells = <1>;
    359. 

  359. -			compatible = "allwinner,sun4i-axi-gates-clk";
    360. 

  360. +			compatible = "allwinner,sun4i-a10-axi-gates-clk";
    361. 

  361.  			reg = <0x01c2005c 0x4>;
    362. 

  362.  			clocks = <&axi>;
    363. 

  363.  			clock-output-names = "axi_dram";
    364. 

  364. @@ -121,7 +121,7 @@
    365. 

  365.  
    366. 

  366.  		ahb: ahb@01c20054 {
    367. 

  367.  			#clock-cells = <0>;
    368. 

  368. -			compatible = "allwinner,sun4i-ahb-clk";
    369. 

  369. +			compatible = "allwinner,sun4i-a10-ahb-clk";
    370. 

  370.  			reg = <0x01c20054 0x4>;
    371. 

  371.  			clocks = <&axi>;
    372. 

  372.  			clock-output-names = "ahb";
    373. 

  373. @@ -143,7 +143,7 @@
    374. 

  374.  
    375. 

  375.  		apb0: apb0@01c20054 {
    376. 

  376.  			#clock-cells = <0>;
    377. 

  377. -			compatible = "allwinner,sun4i-apb0-clk";
    378. 

  378. +			compatible = "allwinner,sun4i-a10-apb0-clk";
    379. 

  379.  			reg = <0x01c20054 0x4>;
    380. 

  380.  			clocks = <&ahb>;
    381. 

  381.  			clock-output-names = "apb0";
    382. 

  382. @@ -160,7 +160,7 @@
    383. 

  383.  
    384. 

  384.  		apb1_mux: apb1_mux@01c20058 {
    385. 

  385.  			#clock-cells = <0>;
    386. 

  386. -			compatible = "allwinner,sun4i-apb1-mux-clk";
    387. 

  387. +			compatible = "allwinner,sun4i-a10-apb1-mux-clk";
    388. 

  388.  			reg = <0x01c20058 0x4>;
    389. 

  389.  			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
    390. 

  390.  			clock-output-names = "apb1_mux";
    391. 

  391. @@ -168,7 +168,7 @@
    392. 

  392.  
    393. 

  393.  		apb1: apb1@01c20058 {
    394. 

  394.  			#clock-cells = <0>;
    395. 

  395. -			compatible = "allwinner,sun4i-apb1-clk";
    396. 

  396. +			compatible = "allwinner,sun4i-a10-apb1-clk";
    397. 

  397.  			reg = <0x01c20058 0x4>;
    398. 

  398.  			clocks = <&apb1_mux>;
    399. 

  399.  			clock-output-names = "apb1";
    400. 

  400. @@ -186,7 +186,7 @@
    401. 

  401.  
    402. 

  402.  		nand_clk: clk@01c20080 {
    403. 

  403.  			#clock-cells = <0>;
    404. 

  404. -			compatible = "allwinner,sun4i-mod0-clk";
    405. 

  405. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    406. 

  406.  			reg = <0x01c20080 0x4>;
    407. 

  407.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    408. 

  408.  			clock-output-names = "nand";
    409. 

  409. @@ -194,7 +194,7 @@
    410. 

  410.  
    411. 

  411.  		ms_clk: clk@01c20084 {
    412. 

  412.  			#clock-cells = <0>;
    413. 

  413. -			compatible = "allwinner,sun4i-mod0-clk";
    414. 

  414. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    415. 

  415.  			reg = <0x01c20084 0x4>;
    416. 

  416.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    417. 

  417.  			clock-output-names = "ms";
    418. 

  418. @@ -202,7 +202,7 @@
    419. 

  419.  
    420. 

  420.  		mmc0_clk: clk@01c20088 {
    421. 

  421.  			#clock-cells = <0>;
    422. 

  422. -			compatible = "allwinner,sun4i-mod0-clk";
    423. 

  423. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    424. 

  424.  			reg = <0x01c20088 0x4>;
    425. 

  425.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    426. 

  426.  			clock-output-names = "mmc0";
    427. 

  427. @@ -210,7 +210,7 @@
    428. 

  428.  
    429. 

  429.  		mmc1_clk: clk@01c2008c {
    430. 

  430.  			#clock-cells = <0>;
    431. 

  431. -			compatible = "allwinner,sun4i-mod0-clk";
    432. 

  432. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    433. 

  433.  			reg = <0x01c2008c 0x4>;
    434. 

  434.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    435. 

  435.  			clock-output-names = "mmc1";
    436. 

  436. @@ -218,7 +218,7 @@
    437. 

  437.  
    438. 

  438.  		mmc2_clk: clk@01c20090 {
    439. 

  439.  			#clock-cells = <0>;
    440. 

  440. -			compatible = "allwinner,sun4i-mod0-clk";
    441. 

  441. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    442. 

  442.  			reg = <0x01c20090 0x4>;
    443. 

  443.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    444. 

  444.  			clock-output-names = "mmc2";
    445. 

  445. @@ -226,7 +226,7 @@
    446. 

  446.  
    447. 

  447.  		ts_clk: clk@01c20098 {
    448. 

  448.  			#clock-cells = <0>;
    449. 

  449. -			compatible = "allwinner,sun4i-mod0-clk";
    450. 

  450. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    451. 

  451.  			reg = <0x01c20098 0x4>;
    452. 

  452.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    453. 

  453.  			clock-output-names = "ts";
    454. 

  454. @@ -234,7 +234,7 @@
    455. 

  455.  
    456. 

  456.  		ss_clk: clk@01c2009c {
    457. 

  457.  			#clock-cells = <0>;
    458. 

  458. -			compatible = "allwinner,sun4i-mod0-clk";
    459. 

  459. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    460. 

  460.  			reg = <0x01c2009c 0x4>;
    461. 

  461.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    462. 

  462.  			clock-output-names = "ss";
    463. 

  463. @@ -242,7 +242,7 @@
    464. 

  464.  
    465. 

  465.  		spi0_clk: clk@01c200a0 {
    466. 

  466.  			#clock-cells = <0>;
    467. 

  467. -			compatible = "allwinner,sun4i-mod0-clk";
    468. 

  468. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    469. 

  469.  			reg = <0x01c200a0 0x4>;
    470. 

  470.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    471. 

  471.  			clock-output-names = "spi0";
    472. 

  472. @@ -250,7 +250,7 @@
    473. 

  473.  
    474. 

  474.  		spi1_clk: clk@01c200a4 {
    475. 

  475.  			#clock-cells = <0>;
    476. 

  476. -			compatible = "allwinner,sun4i-mod0-clk";
    477. 

  477. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    478. 

  478.  			reg = <0x01c200a4 0x4>;
    479. 

  479.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    480. 

  480.  			clock-output-names = "spi1";
    481. 

  481. @@ -258,7 +258,7 @@
    482. 

  482.  
    483. 

  483.  		spi2_clk: clk@01c200a8 {
    484. 

  484.  			#clock-cells = <0>;
    485. 

  485. -			compatible = "allwinner,sun4i-mod0-clk";
    486. 

  486. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    487. 

  487.  			reg = <0x01c200a8 0x4>;
    488. 

  488.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    489. 

  489.  			clock-output-names = "spi2";
    490. 

  490. @@ -266,7 +266,7 @@
    491. 

  491.  
    492. 

  492.  		ir0_clk: clk@01c200b0 {
    493. 

  493.  			#clock-cells = <0>;
    494. 

  494. -			compatible = "allwinner,sun4i-mod0-clk";
    495. 

  495. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    496. 

  496.  			reg = <0x01c200b0 0x4>;
    497. 

  497.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    498. 

  498.  			clock-output-names = "ir0";
    499. 

  499. @@ -283,7 +283,7 @@
    500. 

  500.  
    501. 

  501.  		mbus_clk: clk@01c2015c {
    502. 

  502.  			#clock-cells = <0>;
    503. 

  503. -			compatible = "allwinner,sun4i-mod0-clk";
    504. 

  504. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    505. 

  505.  			reg = <0x01c2015c 0x4>;
    506. 

  506.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    507. 

  507.  			clock-output-names = "mbus";
    508. 

  508. --- a/arch/arm/boot/dts/sun5i-a13.dtsi
    509. 

  509. +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
    510. 

  510. @@ -54,7 +54,7 @@
    511. 

  511.  
    512. 

  512.  		osc24M: clk@01c20050 {
    513. 

  513.  			#clock-cells = <0>;
    514. 

  514. -			compatible = "allwinner,sun4i-osc-clk";
    515. 

  515. +			compatible = "allwinner,sun4i-a10-osc-clk";
    516. 

  516.  			reg = <0x01c20050 0x4>;
    517. 

  517.  			clock-frequency = <24000000>;
    518. 

  518.  			clock-output-names = "osc24M";
    519. 

  519. @@ -69,7 +69,7 @@
    520. 

  520.  
    521. 

  521.  		pll1: clk@01c20000 {
    522. 

  522.  			#clock-cells = <0>;
    523. 

  523. -			compatible = "allwinner,sun4i-pll1-clk";
    524. 

  524. +			compatible = "allwinner,sun4i-a10-pll1-clk";
    525. 

  525.  			reg = <0x01c20000 0x4>;
    526. 

  526.  			clocks = <&osc24M>;
    527. 

  527.  			clock-output-names = "pll1";
    528. 

  528. @@ -77,7 +77,7 @@
    529. 

  529.  
    530. 

  530.  		pll4: clk@01c20018 {
    531. 

  531.  			#clock-cells = <0>;
    532. 

  532. -			compatible = "allwinner,sun4i-pll1-clk";
    533. 

  533. +			compatible = "allwinner,sun4i-a10-pll1-clk";
    534. 

  534.  			reg = <0x01c20018 0x4>;
    535. 

  535.  			clocks = <&osc24M>;
    536. 

  536.  			clock-output-names = "pll4";
    537. 

  537. @@ -85,7 +85,7 @@
    538. 

  538.  
    539. 

  539.  		pll5: clk@01c20020 {
    540. 

  540.  			#clock-cells = <1>;
    541. 

  541. -			compatible = "allwinner,sun4i-pll5-clk";
    542. 

  542. +			compatible = "allwinner,sun4i-a10-pll5-clk";
    543. 

  543.  			reg = <0x01c20020 0x4>;
    544. 

  544.  			clocks = <&osc24M>;
    545. 

  545.  			clock-output-names = "pll5_ddr", "pll5_other";
    546. 

  546. @@ -93,7 +93,7 @@
    547. 

  547.  
    548. 

  548.  		pll6: clk@01c20028 {
    549. 

  549.  			#clock-cells = <1>;
    550. 

  550. -			compatible = "allwinner,sun4i-pll6-clk";
    551. 

  551. +			compatible = "allwinner,sun4i-a10-pll6-clk";
    552. 

  552.  			reg = <0x01c20028 0x4>;
    553. 

  553.  			clocks = <&osc24M>;
    554. 

  554.  			clock-output-names = "pll6_sata", "pll6_other", "pll6";
    555. 

  555. @@ -102,7 +102,7 @@
    556. 

  556.  		/* dummy is 200M */
    557. 

  557.  		cpu: cpu@01c20054 {
    558. 

  558.  			#clock-cells = <0>;
    559. 

  559. -			compatible = "allwinner,sun4i-cpu-clk";
    560. 

  560. +			compatible = "allwinner,sun4i-a10-cpu-clk";
    561. 

  561.  			reg = <0x01c20054 0x4>;
    562. 

  562.  			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
    563. 

  563.  			clock-output-names = "cpu";
    564. 

  564. @@ -110,7 +110,7 @@
    565. 

  565.  
    566. 

  566.  		axi: axi@01c20054 {
    567. 

  567.  			#clock-cells = <0>;
    568. 

  568. -			compatible = "allwinner,sun4i-axi-clk";
    569. 

  569. +			compatible = "allwinner,sun4i-a10-axi-clk";
    570. 

  570.  			reg = <0x01c20054 0x4>;
    571. 

  571.  			clocks = <&cpu>;
    572. 

  572.  			clock-output-names = "axi";
    573. 

  573. @@ -118,7 +118,7 @@
    574. 

  574.  
    575. 

  575.  		axi_gates: clk@01c2005c {
    576. 

  576.  			#clock-cells = <1>;
    577. 

  577. -			compatible = "allwinner,sun4i-axi-gates-clk";
    578. 

  578. +			compatible = "allwinner,sun4i-a10-axi-gates-clk";
    579. 

  579.  			reg = <0x01c2005c 0x4>;
    580. 

  580.  			clocks = <&axi>;
    581. 

  581.  			clock-output-names = "axi_dram";
    582. 

  582. @@ -126,7 +126,7 @@
    583. 

  583.  
    584. 

  584.  		ahb: ahb@01c20054 {
    585. 

  585.  			#clock-cells = <0>;
    586. 

  586. -			compatible = "allwinner,sun4i-ahb-clk";
    587. 

  587. +			compatible = "allwinner,sun4i-a10-ahb-clk";
    588. 

  588.  			reg = <0x01c20054 0x4>;
    589. 

  589.  			clocks = <&axi>;
    590. 

  590.  			clock-output-names = "ahb";
    591. 

  591. @@ -147,7 +147,7 @@
    592. 

  592.  
    593. 

  593.  		apb0: apb0@01c20054 {
    594. 

  594.  			#clock-cells = <0>;
    595. 

  595. -			compatible = "allwinner,sun4i-apb0-clk";
    596. 

  596. +			compatible = "allwinner,sun4i-a10-apb0-clk";
    597. 

  597.  			reg = <0x01c20054 0x4>;
    598. 

  598.  			clocks = <&ahb>;
    599. 

  599.  			clock-output-names = "apb0";
    600. 

  600. @@ -163,7 +163,7 @@
    601. 

  601.  
    602. 

  602.  		apb1_mux: apb1_mux@01c20058 {
    603. 

  603.  			#clock-cells = <0>;
    604. 

  604. -			compatible = "allwinner,sun4i-apb1-mux-clk";
    605. 

  605. +			compatible = "allwinner,sun4i-a10-apb1-mux-clk";
    606. 

  606.  			reg = <0x01c20058 0x4>;
    607. 

  607.  			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
    608. 

  608.  			clock-output-names = "apb1_mux";
    609. 

  609. @@ -171,7 +171,7 @@
    610. 

  610.  
    611. 

  611.  		apb1: apb1@01c20058 {
    612. 

  612.  			#clock-cells = <0>;
    613. 

  613. -			compatible = "allwinner,sun4i-apb1-clk";
    614. 

  614. +			compatible = "allwinner,sun4i-a10-apb1-clk";
    615. 

  615.  			reg = <0x01c20058 0x4>;
    616. 

  616.  			clocks = <&apb1_mux>;
    617. 

  617.  			clock-output-names = "apb1";
    618. 

  618. @@ -188,7 +188,7 @@
    619. 

  619.  
    620. 

  620.  		nand_clk: clk@01c20080 {
    621. 

  621.  			#clock-cells = <0>;
    622. 

  622. -			compatible = "allwinner,sun4i-mod0-clk";
    623. 

  623. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    624. 

  624.  			reg = <0x01c20080 0x4>;
    625. 

  625.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    626. 

  626.  			clock-output-names = "nand";
    627. 

  627. @@ -196,7 +196,7 @@
    628. 

  628.  
    629. 

  629.  		ms_clk: clk@01c20084 {
    630. 

  630.  			#clock-cells = <0>;
    631. 

  631. -			compatible = "allwinner,sun4i-mod0-clk";
    632. 

  632. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    633. 

  633.  			reg = <0x01c20084 0x4>;
    634. 

  634.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    635. 

  635.  			clock-output-names = "ms";
    636. 

  636. @@ -204,7 +204,7 @@
    637. 

  637.  
    638. 

  638.  		mmc0_clk: clk@01c20088 {
    639. 

  639.  			#clock-cells = <0>;
    640. 

  640. -			compatible = "allwinner,sun4i-mod0-clk";
    641. 

  641. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    642. 

  642.  			reg = <0x01c20088 0x4>;
    643. 

  643.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    644. 

  644.  			clock-output-names = "mmc0";
    645. 

  645. @@ -212,7 +212,7 @@
    646. 

  646.  
    647. 

  647.  		mmc1_clk: clk@01c2008c {
    648. 

  648.  			#clock-cells = <0>;
    649. 

  649. -			compatible = "allwinner,sun4i-mod0-clk";
    650. 

  650. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    651. 

  651.  			reg = <0x01c2008c 0x4>;
    652. 

  652.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    653. 

  653.  			clock-output-names = "mmc1";
    654. 

  654. @@ -220,7 +220,7 @@
    655. 

  655.  
    656. 

  656.  		mmc2_clk: clk@01c20090 {
    657. 

  657.  			#clock-cells = <0>;
    658. 

  658. -			compatible = "allwinner,sun4i-mod0-clk";
    659. 

  659. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    660. 

  660.  			reg = <0x01c20090 0x4>;
    661. 

  661.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    662. 

  662.  			clock-output-names = "mmc2";
    663. 

  663. @@ -228,7 +228,7 @@
    664. 

  664.  
    665. 

  665.  		ts_clk: clk@01c20098 {
    666. 

  666.  			#clock-cells = <0>;
    667. 

  667. -			compatible = "allwinner,sun4i-mod0-clk";
    668. 

  668. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    669. 

  669.  			reg = <0x01c20098 0x4>;
    670. 

  670.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    671. 

  671.  			clock-output-names = "ts";
    672. 

  672. @@ -236,7 +236,7 @@
    673. 

  673.  
    674. 

  674.  		ss_clk: clk@01c2009c {
    675. 

  675.  			#clock-cells = <0>;
    676. 

  676. -			compatible = "allwinner,sun4i-mod0-clk";
    677. 

  677. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    678. 

  678.  			reg = <0x01c2009c 0x4>;
    679. 

  679.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    680. 

  680.  			clock-output-names = "ss";
    681. 

  681. @@ -244,7 +244,7 @@
    682. 

  682.  
    683. 

  683.  		spi0_clk: clk@01c200a0 {
    684. 

  684.  			#clock-cells = <0>;
    685. 

  685. -			compatible = "allwinner,sun4i-mod0-clk";
    686. 

  686. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    687. 

  687.  			reg = <0x01c200a0 0x4>;
    688. 

  688.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    689. 

  689.  			clock-output-names = "spi0";
    690. 

  690. @@ -252,7 +252,7 @@
    691. 

  691.  
    692. 

  692.  		spi1_clk: clk@01c200a4 {
    693. 

  693.  			#clock-cells = <0>;
    694. 

  694. -			compatible = "allwinner,sun4i-mod0-clk";
    695. 

  695. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    696. 

  696.  			reg = <0x01c200a4 0x4>;
    697. 

  697.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    698. 

  698.  			clock-output-names = "spi1";
    699. 

  699. @@ -260,7 +260,7 @@
    700. 

  700.  
    701. 

  701.  		spi2_clk: clk@01c200a8 {
    702. 

  702.  			#clock-cells = <0>;
    703. 

  703. -			compatible = "allwinner,sun4i-mod0-clk";
    704. 

  704. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    705. 

  705.  			reg = <0x01c200a8 0x4>;
    706. 

  706.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    707. 

  707.  			clock-output-names = "spi2";
    708. 

  708. @@ -268,7 +268,7 @@
    709. 

  709.  
    710. 

  710.  		ir0_clk: clk@01c200b0 {
    711. 

  711.  			#clock-cells = <0>;
    712. 

  712. -			compatible = "allwinner,sun4i-mod0-clk";
    713. 

  713. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    714. 

  714.  			reg = <0x01c200b0 0x4>;
    715. 

  715.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    716. 

  716.  			clock-output-names = "ir0";
    717. 

  717. @@ -285,7 +285,7 @@
    718. 

  718.  
    719. 

  719.  		mbus_clk: clk@01c2015c {
    720. 

  720.  			#clock-cells = <0>;
    721. 

  721. -			compatible = "allwinner,sun4i-mod0-clk";
    722. 

  722. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    723. 

  723.  			reg = <0x01c2015c 0x4>;
    724. 

  724.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    725. 

  725.  			clock-output-names = "mbus";
    726. 

  726. --- a/arch/arm/boot/dts/sun6i-a31.dtsi
    727. 

  727. +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
    728. 

  728. @@ -95,7 +95,7 @@
    729. 

  729.  
    730. 

  730.  		cpu: cpu@01c20050 {
    731. 

  731.  			#clock-cells = <0>;
    732. 

  732. -			compatible = "allwinner,sun4i-cpu-clk";
    733. 

  733. +			compatible = "allwinner,sun4i-a10-cpu-clk";
    734. 

  734.  			reg = <0x01c20050 0x4>;
    735. 

  735.  
    736. 

  736.  			/*
    737. 

  737. @@ -110,7 +110,7 @@
    738. 

  738.  
    739. 

  739.  		axi: axi@01c20050 {
    740. 

  740.  			#clock-cells = <0>;
    741. 

  741. -			compatible = "allwinner,sun4i-axi-clk";
    742. 

  742. +			compatible = "allwinner,sun4i-a10-axi-clk";
    743. 

  743.  			reg = <0x01c20050 0x4>;
    744. 

  744.  			clocks = <&cpu>;
    745. 

  745.  			clock-output-names = "axi";
    746. 

  746. @@ -126,7 +126,7 @@
    747. 

  747.  
    748. 

  748.  		ahb1: ahb1@01c20054 {
    749. 

  749.  			#clock-cells = <0>;
    750. 

  750. -			compatible = "allwinner,sun4i-ahb-clk";
    751. 

  751. +			compatible = "allwinner,sun4i-a10-ahb-clk";
    752. 

  752.  			reg = <0x01c20054 0x4>;
    753. 

  753.  			clocks = <&ahb1_mux>;
    754. 

  754.  			clock-output-names = "ahb1";
    755. 

  755. @@ -155,7 +155,7 @@
    756. 

  756.  
    757. 

  757.  		apb1: apb1@01c20054 {
    758. 

  758.  			#clock-cells = <0>;
    759. 

  759. -			compatible = "allwinner,sun4i-apb0-clk";
    760. 

  760. +			compatible = "allwinner,sun4i-a10-apb0-clk";
    761. 

  761.  			reg = <0x01c20054 0x4>;
    762. 

  762.  			clocks = <&ahb1>;
    763. 

  763.  			clock-output-names = "apb1";
    764. 

  764. @@ -173,7 +173,7 @@
    765. 

  765.  
    766. 

  766.  		apb2_mux: apb2_mux@01c20058 {
    767. 

  767.  			#clock-cells = <0>;
    768. 

  768. -			compatible = "allwinner,sun4i-apb1-mux-clk";
    769. 

  769. +			compatible = "allwinner,sun4i-a10-apb1-mux-clk";
    770. 

  770.  			reg = <0x01c20058 0x4>;
    771. 

  771.  			clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
    772. 

  772.  			clock-output-names = "apb2_mux";
    773. 

  773. --- a/arch/arm/boot/dts/sun7i-a20.dtsi
    774. 

  774. +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
    775. 

  775. @@ -64,7 +64,7 @@
    776. 

  776.  
    777. 

  777.  		osc24M: clk@01c20050 {
    778. 

  778.  			#clock-cells = <0>;
    779. 

  779. -			compatible = "allwinner,sun4i-osc-clk";
    780. 

  780. +			compatible = "allwinner,sun4i-a10-osc-clk";
    781. 

  781.  			reg = <0x01c20050 0x4>;
    782. 

  782.  			clock-frequency = <24000000>;
    783. 

  783.  			clock-output-names = "osc24M";
    784. 

  784. @@ -79,7 +79,7 @@
    785. 

  785.  
    786. 

  786.  		pll1: clk@01c20000 {
    787. 

  787.  			#clock-cells = <0>;
    788. 

  788. -			compatible = "allwinner,sun4i-pll1-clk";
    789. 

  789. +			compatible = "allwinner,sun4i-a10-pll1-clk";
    790. 

  790.  			reg = <0x01c20000 0x4>;
    791. 

  791.  			clocks = <&osc24M>;
    792. 

  792.  			clock-output-names = "pll1";
    793. 

  793. @@ -87,7 +87,7 @@
    794. 

  794.  
    795. 

  795.  		pll4: clk@01c20018 {
    796. 

  796.  			#clock-cells = <0>;
    797. 

  797. -			compatible = "allwinner,sun4i-pll1-clk";
    798. 

  798. +			compatible = "allwinner,sun4i-a10-pll1-clk";
    799. 

  799.  			reg = <0x01c20018 0x4>;
    800. 

  800.  			clocks = <&osc24M>;
    801. 

  801.  			clock-output-names = "pll4";
    802. 

  802. @@ -95,7 +95,7 @@
    803. 

  803.  
    804. 

  804.  		pll5: clk@01c20020 {
    805. 

  805.  			#clock-cells = <1>;
    806. 

  806. -			compatible = "allwinner,sun4i-pll5-clk";
    807. 

  807. +			compatible = "allwinner,sun4i-a10-pll5-clk";
    808. 

  808.  			reg = <0x01c20020 0x4>;
    809. 

  809.  			clocks = <&osc24M>;
    810. 

  810.  			clock-output-names = "pll5_ddr", "pll5_other";
    811. 

  811. @@ -103,7 +103,7 @@
    812. 

  812.  
    813. 

  813.  		pll6: clk@01c20028 {
    814. 

  814.  			#clock-cells = <1>;
    815. 

  815. -			compatible = "allwinner,sun4i-pll6-clk";
    816. 

  816. +			compatible = "allwinner,sun4i-a10-pll6-clk";
    817. 

  817.  			reg = <0x01c20028 0x4>;
    818. 

  818.  			clocks = <&osc24M>;
    819. 

  819.  			clock-output-names = "pll6_sata", "pll6_other", "pll6";
    820. 

  820. @@ -111,7 +111,7 @@
    821. 

  821.  
    822. 

  822.  		cpu: cpu@01c20054 {
    823. 

  823.  			#clock-cells = <0>;
    824. 

  824. -			compatible = "allwinner,sun4i-cpu-clk";
    825. 

  825. +			compatible = "allwinner,sun4i-a10-cpu-clk";
    826. 

  826.  			reg = <0x01c20054 0x4>;
    827. 

  827.  			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
    828. 

  828.  			clock-output-names = "cpu";
    829. 

  829. @@ -119,7 +119,7 @@
    830. 

  830.  
    831. 

  831.  		axi: axi@01c20054 {
    832. 

  832.  			#clock-cells = <0>;
    833. 

  833. -			compatible = "allwinner,sun4i-axi-clk";
    834. 

  834. +			compatible = "allwinner,sun4i-a10-axi-clk";
    835. 

  835.  			reg = <0x01c20054 0x4>;
    836. 

  836.  			clocks = <&cpu>;
    837. 

  837.  			clock-output-names = "axi";
    838. 

  838. @@ -127,7 +127,7 @@
    839. 

  839.  
    840. 

  840.  		ahb: ahb@01c20054 {
    841. 

  841.  			#clock-cells = <0>;
    842. 

  842. -			compatible = "allwinner,sun4i-ahb-clk";
    843. 

  843. +			compatible = "allwinner,sun4i-a10-ahb-clk";
    844. 

  844.  			reg = <0x01c20054 0x4>;
    845. 

  845.  			clocks = <&axi>;
    846. 

  846.  			clock-output-names = "ahb";
    847. 

  847. @@ -155,7 +155,7 @@
    848. 

  848.  
    849. 

  849.  		apb0: apb0@01c20054 {
    850. 

  850.  			#clock-cells = <0>;
    851. 

  851. -			compatible = "allwinner,sun4i-apb0-clk";
    852. 

  852. +			compatible = "allwinner,sun4i-a10-apb0-clk";
    853. 

  853.  			reg = <0x01c20054 0x4>;
    854. 

  854.  			clocks = <&ahb>;
    855. 

  855.  			clock-output-names = "apb0";
    856. 

  856. @@ -174,7 +174,7 @@
    857. 

  857.  
    858. 

  858.  		apb1_mux: apb1_mux@01c20058 {
    859. 

  859.  			#clock-cells = <0>;
    860. 

  860. -			compatible = "allwinner,sun4i-apb1-mux-clk";
    861. 

  861. +			compatible = "allwinner,sun4i-a10-apb1-mux-clk";
    862. 

  862.  			reg = <0x01c20058 0x4>;
    863. 

  863.  			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
    864. 

  864.  			clock-output-names = "apb1_mux";
    865. 

  865. @@ -182,7 +182,7 @@
    866. 

  866.  
    867. 

  867.  		apb1: apb1@01c20058 {
    868. 

  868.  			#clock-cells = <0>;
    869. 

  869. -			compatible = "allwinner,sun4i-apb1-clk";
    870. 

  870. +			compatible = "allwinner,sun4i-a10-apb1-clk";
    871. 

  871.  			reg = <0x01c20058 0x4>;
    872. 

  872.  			clocks = <&apb1_mux>;
    873. 

  873.  			clock-output-names = "apb1";
    874. 

  874. @@ -203,7 +203,7 @@
    875. 

  875.  
    876. 

  876.  		nand_clk: clk@01c20080 {
    877. 

  877.  			#clock-cells = <0>;
    878. 

  878. -			compatible = "allwinner,sun4i-mod0-clk";
    879. 

  879. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    880. 

  880.  			reg = <0x01c20080 0x4>;
    881. 

  881.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    882. 

  882.  			clock-output-names = "nand";
    883. 

  883. @@ -211,7 +211,7 @@
    884. 

  884.  
    885. 

  885.  		ms_clk: clk@01c20084 {
    886. 

  886.  			#clock-cells = <0>;
    887. 

  887. -			compatible = "allwinner,sun4i-mod0-clk";
    888. 

  888. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    889. 

  889.  			reg = <0x01c20084 0x4>;
    890. 

  890.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    891. 

  891.  			clock-output-names = "ms";
    892. 

  892. @@ -219,7 +219,7 @@
    893. 

  893.  
    894. 

  894.  		mmc0_clk: clk@01c20088 {
    895. 

  895.  			#clock-cells = <0>;
    896. 

  896. -			compatible = "allwinner,sun4i-mod0-clk";
    897. 

  897. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    898. 

  898.  			reg = <0x01c20088 0x4>;
    899. 

  899.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    900. 

  900.  			clock-output-names = "mmc0";
    901. 

  901. @@ -227,7 +227,7 @@
    902. 

  902.  
    903. 

  903.  		mmc1_clk: clk@01c2008c {
    904. 

  904.  			#clock-cells = <0>;
    905. 

  905. -			compatible = "allwinner,sun4i-mod0-clk";
    906. 

  906. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    907. 

  907.  			reg = <0x01c2008c 0x4>;
    908. 

  908.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    909. 

  909.  			clock-output-names = "mmc1";
    910. 

  910. @@ -235,7 +235,7 @@
    911. 

  911.  
    912. 

  912.  		mmc2_clk: clk@01c20090 {
    913. 

  913.  			#clock-cells = <0>;
    914. 

  914. -			compatible = "allwinner,sun4i-mod0-clk";
    915. 

  915. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    916. 

  916.  			reg = <0x01c20090 0x4>;
    917. 

  917.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    918. 

  918.  			clock-output-names = "mmc2";
    919. 

  919. @@ -243,7 +243,7 @@
    920. 

  920.  
    921. 

  921.  		mmc3_clk: clk@01c20094 {
    922. 

  922.  			#clock-cells = <0>;
    923. 

  923. -			compatible = "allwinner,sun4i-mod0-clk";
    924. 

  924. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    925. 

  925.  			reg = <0x01c20094 0x4>;
    926. 

  926.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    927. 

  927.  			clock-output-names = "mmc3";
    928. 

  928. @@ -251,7 +251,7 @@
    929. 

  929.  
    930. 

  930.  		ts_clk: clk@01c20098 {
    931. 

  931.  			#clock-cells = <0>;
    932. 

  932. -			compatible = "allwinner,sun4i-mod0-clk";
    933. 

  933. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    934. 

  934.  			reg = <0x01c20098 0x4>;
    935. 

  935.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    936. 

  936.  			clock-output-names = "ts";
    937. 

  937. @@ -259,7 +259,7 @@
    938. 

  938.  
    939. 

  939.  		ss_clk: clk@01c2009c {
    940. 

  940.  			#clock-cells = <0>;
    941. 

  941. -			compatible = "allwinner,sun4i-mod0-clk";
    942. 

  942. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    943. 

  943.  			reg = <0x01c2009c 0x4>;
    944. 

  944.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    945. 

  945.  			clock-output-names = "ss";
    946. 

  946. @@ -267,7 +267,7 @@
    947. 

  947.  
    948. 

  948.  		spi0_clk: clk@01c200a0 {
    949. 

  949.  			#clock-cells = <0>;
    950. 

  950. -			compatible = "allwinner,sun4i-mod0-clk";
    951. 

  951. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    952. 

  952.  			reg = <0x01c200a0 0x4>;
    953. 

  953.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    954. 

  954.  			clock-output-names = "spi0";
    955. 

  955. @@ -275,7 +275,7 @@
    956. 

  956.  
    957. 

  957.  		spi1_clk: clk@01c200a4 {
    958. 

  958.  			#clock-cells = <0>;
    959. 

  959. -			compatible = "allwinner,sun4i-mod0-clk";
    960. 

  960. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    961. 

  961.  			reg = <0x01c200a4 0x4>;
    962. 

  962.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    963. 

  963.  			clock-output-names = "spi1";
    964. 

  964. @@ -283,7 +283,7 @@
    965. 

  965.  
    966. 

  966.  		spi2_clk: clk@01c200a8 {
    967. 

  967.  			#clock-cells = <0>;
    968. 

  968. -			compatible = "allwinner,sun4i-mod0-clk";
    969. 

  969. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    970. 

  970.  			reg = <0x01c200a8 0x4>;
    971. 

  971.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    972. 

  972.  			clock-output-names = "spi2";
    973. 

  973. @@ -291,7 +291,7 @@
    974. 

  974.  
    975. 

  975.  		pata_clk: clk@01c200ac {
    976. 

  976.  			#clock-cells = <0>;
    977. 

  977. -			compatible = "allwinner,sun4i-mod0-clk";
    978. 

  978. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    979. 

  979.  			reg = <0x01c200ac 0x4>;
    980. 

  980.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    981. 

  981.  			clock-output-names = "pata";
    982. 

  982. @@ -299,7 +299,7 @@
    983. 

  983.  
    984. 

  984.  		ir0_clk: clk@01c200b0 {
    985. 

  985.  			#clock-cells = <0>;
    986. 

  986. -			compatible = "allwinner,sun4i-mod0-clk";
    987. 

  987. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    988. 

  988.  			reg = <0x01c200b0 0x4>;
    989. 

  989.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    990. 

  990.  			clock-output-names = "ir0";
    991. 

  991. @@ -307,7 +307,7 @@
    992. 

  992.  
    993. 

  993.  		ir1_clk: clk@01c200b4 {
    994. 

  994.  			#clock-cells = <0>;
    995. 

  995. -			compatible = "allwinner,sun4i-mod0-clk";
    996. 

  996. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    997. 

  997.  			reg = <0x01c200b4 0x4>;
    998. 

  998.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    999. 

  999.  			clock-output-names = "ir1";
    1000. 

  1000. @@ -324,7 +324,7 @@
    1001. 

  1001.  
    1002. 

  1002.  		spi3_clk: clk@01c200d4 {
    1003. 

  1003.  			#clock-cells = <0>;
    1004. 

  1004. -			compatible = "allwinner,sun4i-mod0-clk";
    1005. 

  1005. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    1006. 

  1006.  			reg = <0x01c200d4 0x4>;
    1007. 

  1007.  			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
    1008. 

  1008.  			clock-output-names = "spi3";
    1009. 

  1009. @@ -332,7 +332,7 @@
    1010. 

  1010.  
    1011. 

  1011.  		mbus_clk: clk@01c2015c {
    1012. 

  1012.  			#clock-cells = <0>;
    1013. 

  1013. -			compatible = "allwinner,sun4i-mod0-clk";
    1014. 

  1014. +			compatible = "allwinner,sun4i-a10-mod0-clk";
    1015. 

  1015.  			reg = <0x01c2015c 0x4>;
    1016. 

  1016.  			clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
    1017. 

  1017.  			clock-output-names = "mbus";
    1018.