206-dt-sun67i-add-nmi-irqchip.patch 1.3 KB

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  1. From eebb592523672ee7288b9327bd222165db638d1a Mon Sep 17 00:00:00 2001
  2. From: Carlo Caione <carlo@caione.org>
  3. Date: Thu, 27 Feb 2014 20:34:21 +0100
  4. Subject: [PATCH] ARM: sun7i/sun6i: dts: Add NMI irqchip support
  5. This patch adds DTS entries for NMI controller as child of GIC.
  6. Signed-off-by: Carlo Caione <carlo@caione.org>
  7. ---
  8. arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++++++++
  9. arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
  10. 2 files changed, 16 insertions(+)
  11. --- a/arch/arm/boot/dts/sun6i-a31.dtsi
  12. +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
  13. @@ -370,6 +370,14 @@
  14. interrupts = <1 9 0xf04>;
  15. };
  16. + nmi_intc: interrupt-controller@01f00c0c {
  17. + compatible = "allwinner,sun6i-a31-sc-nmi";
  18. + interrupt-controller;
  19. + #interrupt-cells = <2>;
  20. + reg = <0x01f00c0c 0x38>;
  21. + interrupts = <0 32 4>;
  22. + };
  23. +
  24. cpucfg@01f01c00 {
  25. compatible = "allwinner,sun6i-a31-cpuconfig";
  26. reg = <0x01f01c00 0x300>;
  27. --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  28. +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  29. @@ -401,6 +401,14 @@
  30. #size-cells = <1>;
  31. ranges;
  32. + nmi_intc: interrupt-controller@01c00030 {
  33. + compatible = "allwinner,sun7i-a20-sc-nmi";
  34. + interrupt-controller;
  35. + #interrupt-cells = <2>;
  36. + reg = <0x01c00030 0x0c>;
  37. + interrupts = <0 0 4>;
  38. + };
  39. +
  40. spi0: spi@01c05000 {
  41. compatible = "allwinner,sun4i-a10-spi";
  42. reg = <0x01c05000 0x1000>;