Bump tsc rate to 1Ghz

src/config.js

@@ -56,7 +56,7 @@ var TIME_PER_FRAME = 1;
  * @const
  * How many ticks the TSC does per millisecond
  */
-var TSC_RATE = 50 * 1000;
+var TSC_RATE = 1 * 1000 * 1000;
 
 
 /** @const */

src/cpu.js

@@ -1986,6 +1986,7 @@ CPU.prototype.cpuid = function()
             eax = 1; // denominator
             ebx = 1; // numerator
             ecx = TSC_RATE * 1000; // core crystal clock frequency in Hz
+            dbg_assert((ecx >>> 0) === ecx);
             //  (TSC frequency = core crystal clock frequency * EBX/EAX)
             break;
 
@@ -1993,10 +1994,15 @@ CPU.prototype.cpuid = function()
             eax = Math.floor(TSC_RATE / 1000); // core base frequency in MHz
             ebx = Math.floor(TSC_RATE / 1000); // core maximum frequency in MHz
             ecx = 10; // bus (reference) frequency in MHz
+
+            // 16-bit values
+            dbg_assert(eax < 0x10000);
+            dbg_assert(ebx < 0x10000);
+            dbg_assert(ecx < 0x10000);
             break;
 
         default:
-            dbg_log("cpuid: unimplemented eax: " + h(this.reg32[reg_eax]), LOG_CPU);
+            dbg_log("cpuid: unimplemented eax: " + h(this.reg32[reg_eax] >>> 0), LOG_CPU);
     }
 
     if(level === 4)

src/rust/cpu2/cpu.rs

@@ -229,9 +229,11 @@ pub const CPU_EXCEPTION_MC: i32 = 18;
 pub const CPU_EXCEPTION_XM: i32 = 19;
 pub const CPU_EXCEPTION_VE: i32 = 20;
 pub const CHECK_TLB_INVARIANTS: bool = false;
+
 pub const DEBUG: bool = cfg!(debug_assertions);
+
 pub const LOOP_COUNTER: i32 = 20011;
-pub const TSC_RATE: f64 = (50 * 1000) as f64;
+pub const TSC_RATE: f64 = 1_000_000.0;
 
 pub static mut jit_block_boundary: bool = false;