 Fabian
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3a8d644d75
Port jit to Rust
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5 years ago |
 Awal Garg
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03f0da9525
use wg_ prefix for wasmgen, add tests to makefile
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5 years ago |
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Fabian
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9b2b3250df
Fix 8-bit jumps in 16-bit mode
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5 years ago |
 Amaan Cheval
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80c9cdb9c1
codegen/gen_safe_write32: Use local-variable based arg passing
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6 years ago |
|
Amaan Cheval
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83e585c123
jit/instructions: Inline 0x89 "mov [mem], reg" for generated WASM
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6 years ago |
|
Amaan Cheval
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5abcffd916
codegen: gen_store instead of gen_set_reg32_from_stack
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6 years ago |
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Amaan Cheval
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db166cd703
jit/instructions: Inline 0x8b "mov reg, [mem]" for generated WASM
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6 years ago |
|
Amaan Cheval
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af157ff91f
instructions/codegen: Remove unnecessary helper function and comment
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6 years ago |
|
Amaan Cheval
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8741c28524
codegen/jit: Optimize "mov reg, reg" with direct load/stores
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6 years ago |
|
Amaan Cheval
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cde8a2d005
codegen: s/gen_fn[0-9]/gen_fn[0-9]_const/ to indicate inline args
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6 years ago |
|
Amaan Cheval
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ebe7b3d426
codegen: s/gen_reg*_eq/gen_set_reg*/
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6 years ago |
|
Amaan Cheval
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0d5621f2c0
instructions: Uninline gen_mov{16,32}_r helper functions
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6 years ago |
|
Amaan Cheval
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2128f07796
jit: Inline 0x89 and 0x8b opcodes's reg variants
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6 years ago |
|
Fabian
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39d8d17031
Make 8f custom, simplify generate_jit by removing handling of requires_prefix_call
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6 years ago |
|
Fabian
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f8349af093
New block analysis, generation of state machine with multiple basic blocks
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6 years ago |
|
Amaan Cheval
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17a442314d
cpu/instructions: Remove diverged, branch_taken, branch_not_taken
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6 years ago |
|
Amaan Cheval
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dffca42ca7
instructions: Call after_block_boundary from interpreter not instr
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6 years ago |
|
Amaan Cheval
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41c8241d5e
x86_table: Mark state-altering instructions as JIT block boundaries
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6 years ago |
|
Fabian
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54bb73e7f9
Delete fpu_truncate, use trunc
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6 years ago |
|
Amaan Cheval
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5afa523a1c
fpu: Get rid of fpu_op_D9_*_reg functions
|
6 years ago |
|
Amaan Cheval
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0607bd741c
fpu: refactor functions fpu_[arith] functions to accept target index first
|
6 years ago |
|
Amaan Cheval
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7f306f442c
fpu instructions: Refactor to have instruction definitions in 1 line
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6 years ago |
|
Amaan Cheval
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2005f6e257
fpu: Refactor to make function names more specific
|
6 years ago |
|
Amaan Cheval
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1f0e7c3ce0
fpu: Have opcode 0xDF use fixed_g instruction functions
|
6 years ago |
|
Amaan Cheval
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76c4767d7e
fpu: s/fpu_fnstsw/fpu_fnstsw_mem/
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6 years ago |
|
Amaan Cheval
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fca80793b8
fpu: Have opcode 0xDE use fixed_g instruction functions
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6 years ago |
|
Amaan Cheval
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fbb4817b5f
instructions: brace formatting
|
6 years ago |
|
Amaan Cheval
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4910777084
fpu: Have opcode 0xDD use fixed_g instruction functions
|
6 years ago |
|
Amaan Cheval
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9147787523
fpu: Add FPU functions for fld in op 0xDB instead of implementing inline
|
6 years ago |
|
Amaan Cheval
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33c2b72553
fpu: Have opcode 0xDC use fixed_g instruction functions
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6 years ago |
