 Fabian
|
37c3d1f83c
Generate direct control flow, using wasm blocks and loops
|
il y a 3 ans |
|
Fabian
|
9853bdb868
Merge 16-bit and 32-bit 0f tables (saves 200kB on v86.wasm)
|
il y a 3 ans |
|
Fabian
|
11dfeb1ee7
Fix minor descrepancy between analyser and jit
|
il y a 3 ans |
|
Fabian
|
a26eb43719
Fix: Inhibit interrupts for one instruction after STI (fixes ReactOS)
|
il y a 3 ans |
|
Fabian
|
acb8ad5423
Avoid console.assert (doesn't throw)
|
il y a 3 ans |
|
Fabian
|
a73988a817
Make loop, loopz, loopnz and jcxz custom generated
|
il y a 3 ans |
|
Fabian
|
c207400922
Fix Rust warnings
|
il y a 3 ans |
|
Fabian
|
4bb3c14e57
Comment
|
il y a 3 ans |
|
Fabian
|
0263764a5c
Remove unused unguarded_register property during analysis
|
il y a 3 ans |
|
Fabian
|
a8308b988d
Store registers in locals
|
il y a 5 ans |
|
Fabian
|
440b67eda5
Support for gen_safe_write128 and code generation for MOVAPS/MOVDQA (0F29/660F7F)
|
il y a 5 ans |
|
Fabian
|
ec059a9f27
Codegen for fpu instructions (D8 group)
|
il y a 5 ans |
|
Fabian
|
a5cbf53da5
Fix jit in presence of new page fault handling
|
il y a 6 ans |
|
Fabian
|
1253b72906
Generate prefix handling for string instructions
|
il y a 6 ans |
|
Fabian
|
3a8d644d75
Port jit to Rust
|
il y a 6 ans |
|
Fabian
|
2609041e64
Don't fail when invalid instructions are analyzed/jitted
|
il y a 6 ans |
|
Fabian
|
cba5491fc4
Multiple jit block entry points
|
il y a 6 ans |
|
Fabian
|
ded423b1c5
x86 table: Add remaining 0f instructions, simplify gen scripts
|
il y a 6 ans |
|
Fabian
|
a9b5f153a8
Move around and add some assertions
|
il y a 6 ans |
|
Fabian
|
65bf2e350d
Don't generate duplicate flags checks
|
il y a 6 ans |
|
Fabian
|
f8349af093
New block analysis, generation of state machine with multiple basic blocks
|
il y a 6 ans |
