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kinetis_hw.c 11 KB

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  1. /* kinetis_hw.c
  2. *
  3. * Copyright (C) 2006-2023 wolfSSL Inc.
  4. *
  5. * This file is part of wolfSSL.
  6. *
  7. * wolfSSL is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * wolfSSL is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
  20. */
  21. #include "hw.h"
  22. #include "user_settings.h"
  23. #if defined(FREESCALE) && defined(K_SERIES)
  24. /**********************************************
  25. * NOTE: Customize for actual hardware
  26. **********************************************/
  27. // CPU include for Rowley CrossWorks packages
  28. // $(TargetsDir) location:
  29. // On Mac OS/X: Users/USERNAME/Library/Rowley Associates Limited/CrossWorks for ARM/packages/targets/
  30. // On Windows: C:/Users/USERNAME/Application Data/Local/Rowley Associates Limited/CrossWorks for ARM/packages/targets/
  31. // On Linux: home/USERNAME/.rowley_associates_limited/CrossWorks for ARM/v4/packages/targets/
  32. // Located in $(TargetsDir)/Kinetis/CMSIS/
  33. #ifdef FREESCALE_KSDK_BM
  34. #include "fsl_common.h"
  35. #include "fsl_debug_console.h"
  36. #include "fsl_rtc.h"
  37. #include "fsl_trng.h"
  38. #include "fsl_lpuart.h"
  39. #include "fsl_port.h"
  40. #include "clock_config.h"
  41. #else
  42. #include <MK64F12.h> // Located in $(TargetsDir)/Kinetis/CMSIS/
  43. #endif
  44. // System clock
  45. #ifdef FREESCALE_KSDK_BM
  46. #define SYS_CLK_HZ SystemCoreClock
  47. #else
  48. #define SYS_CLK_HZ 96000000ul /* Core system clock in Hz */
  49. #define SYS_CLK_DRS MCG_C4_DRST_DRS(0x03) /* DRS 0=24MHz, 1=48MHz, 2=72MHz, 3=96MHz */
  50. #define SYS_CLK_DMX MCG_C4_DMX32_MASK /* 0=Disable DMX32 (lower actual speed), MCG_C4_DMX32_MASK=Enable DMX32 */
  51. #define SYS_CLK_DIV 1 /* System clock divisor */
  52. #define BUS_CLK_DIV 2 /* Bus clock divisor */
  53. #define BUS_CLK_KHZ (SYS_CLK_HZ/BUS_CLK_DIV) /* Helper to calculate bus speed for UART */
  54. #define FLASH_CLK_DIV 4 /* Flash clock divisor */
  55. #endif
  56. // UART TX Port, Pin, Mux and Baud
  57. #ifdef FREESCALE_KSDK_BM
  58. #define UART_PORT LPUART4 /* UART Port */
  59. #define UART_TX_PORT PORTC /* UART TX Port */
  60. #define UART_TX_PIN 15U /* UART TX Pin */
  61. #define UART_TX_MUX kPORT_MuxAlt3 /* Kinetis UART pin mux */
  62. #elif defined (WOLFSSL_FRDM_K64)
  63. #define UART_PORT UART0 /* UART Port */
  64. #define UART_TX_PORT PORTB /* UART TX Port */
  65. #define UART_TX_PIN 17U /* UART TX Pin */
  66. #define UART_TX_MUX 0x3 /* Kinetis UART pin mux */
  67. #else
  68. #define UART_PORT UART4 /* UART Port */
  69. #define UART_TX_PORT PORTE /* UART TX Port */
  70. #define UART_TX_PIN 24U /* UART TX Pin */
  71. #define UART_TX_MUX 0x3 /* Kinetis UART pin mux */
  72. #endif
  73. #define UART_BAUD_RATE 115200 /* UART Baud Rate */
  74. #ifdef WOLFSSL_FRDM_K64
  75. #define UART_BAUD UART_BAUD_RATE*8
  76. #else
  77. #define UART_BAUD UART_BAUD_RATE
  78. #endif
  79. /* Note: You will also need to update the UART clock gate in hw_uart_init (SIM_SCGC1_UART5_MASK) */
  80. /* Note: TWR-K60 is UART3, PTC17 */
  81. /* Note: FRDM-K64 is UART4, PTE24 or UART0 PTB17 for OpenOCD (SIM_SCGC4_UART0_MASK)*/
  82. /* Note: TWR-K64 is UART5, PTE8 */
  83. /* Note: FRDM-K82F is LPUART4 PTC15 Alt3 (OpenOCD UART) */
  84. /***********************************************/
  85. // Private functions
  86. static uint32_t mDelayCyclesPerUs = 0;
  87. #define NOP_FOR_LOOP_INSTRUCTION_COUNT 6
  88. static void delay_nop(uint32_t count)
  89. {
  90. int i;
  91. for(i=0; i<count; i++) {
  92. __asm volatile("nop");
  93. }
  94. }
  95. static void hw_mcg_init(void)
  96. {
  97. #ifdef FREESCALE_KSDK_BM
  98. BOARD_BootClockHSRUN();
  99. #else
  100. /* Adjust clock dividers (core/system=div/1, bus=div/2, flex bus=div/2, flash=div/4) */
  101. SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(SYS_CLK_DIV-1) | SIM_CLKDIV1_OUTDIV2(BUS_CLK_DIV-1) |
  102. SIM_CLKDIV1_OUTDIV3(BUS_CLK_DIV-1) | SIM_CLKDIV1_OUTDIV4(FLASH_CLK_DIV-1);
  103. /* Configure FEI internal clock speed */
  104. MCG->C4 = (SYS_CLK_DMX | SYS_CLK_DRS);
  105. while((MCG->C4 & (MCG_C4_DRST_DRS_MASK | MCG_C4_DMX32_MASK)) != (SYS_CLK_DMX | SYS_CLK_DRS));
  106. #endif
  107. }
  108. static void hw_gpio_init(void)
  109. {
  110. #ifdef FREESCALE_KSDK_BM
  111. CLOCK_EnableClock(kCLOCK_PortA);
  112. CLOCK_EnableClock(kCLOCK_PortB);
  113. CLOCK_EnableClock(kCLOCK_PortC);
  114. CLOCK_EnableClock(kCLOCK_PortD);
  115. CLOCK_EnableClock(kCLOCK_PortE);
  116. #else
  117. /* Enable clocks to all GPIO ports */
  118. SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK
  119. #ifdef SIM_SCGC5_PORTC_MASK
  120. | SIM_SCGC5_PORTC_MASK
  121. #endif
  122. #ifdef SIM_SCGC5_PORTD_MASK
  123. | SIM_SCGC5_PORTD_MASK
  124. #endif
  125. #ifdef SIM_SCGC5_PORTE_MASK
  126. | SIM_SCGC5_PORTE_MASK
  127. #endif
  128. );
  129. #if 0 /* Debug clock */
  130. /* ClockOut on PTC3 */
  131. PORTC->PCR[3] = PORT_PCR_MUX(0x05); /* Alt 5 */
  132. SIM_SOPT2 |= SIM_SOPT2_CLKOUTSEL(0); /* FlexBus CLKOUT */
  133. #endif
  134. #endif
  135. }
  136. static void hw_uart_init(void)
  137. {
  138. #ifdef FREESCALE_KSDK_BM
  139. PORT_SetPinMux(UART_TX_PORT, UART_TX_PIN, UART_TX_MUX);
  140. CLOCK_SetLpuartClock(1); /* MCGPLLCLK */
  141. DbgConsole_Init((uint32_t)UART_PORT, UART_BAUD, DEBUG_CONSOLE_DEVICE_TYPE_LPUART, SYS_CLK_HZ);
  142. #else
  143. register uint16_t sbr, brfa;
  144. uint8_t temp;
  145. #ifdef WOLFSSL_FRDM_K64
  146. /* Enable UART core clock ONLY for FRDM-K64F */
  147. SIM->SCGC4 |= SIM_SCGC4_UART0_MASK;
  148. #else
  149. /* Enable UART core clock */
  150. /* Note: Remember to update me if UART_PORT changes */
  151. SIM->SCGC1 |= SIM_SCGC1_UART4_MASK;
  152. #endif
  153. /* Configure UART TX pin */
  154. UART_TX_PORT->PCR[UART_TX_PIN] = PORT_PCR_MUX(UART_TX_MUX);
  155. /* Disable transmitter and receiver while we change settings. */
  156. UART_PORT->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK );
  157. /* Configure the UART for 8-bit mode, no parity */
  158. UART_PORT->C1 = 0;
  159. /* Calculate baud settings */
  160. sbr = (uint16_t)((BUS_CLK_KHZ * 1000)/(UART_BAUD * 16));
  161. temp = UART_PORT->BDH & ~(UART_BDH_SBR(0x1F));
  162. UART_PORT->BDH = temp | UART_BDH_SBR(((sbr & 0x1F00) >> 8));
  163. UART_PORT->BDL = (uint8_t)(sbr & UART_BDL_SBR_MASK);
  164. /* Determine if a fractional divider is needed to get closer to the baud rate */
  165. brfa = (((BUS_CLK_KHZ * 32000)/(UART_BAUD * 16)) - (sbr * 32));
  166. temp = UART_PORT->C4 & ~(UART_C4_BRFA(0x1F));
  167. UART_PORT->C4 = temp | UART_C4_BRFA(brfa);
  168. /* Enable receiver and transmitter */
  169. UART_PORT->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK);
  170. #endif
  171. }
  172. static void hw_rtc_init(void)
  173. {
  174. /* Init nop delay */
  175. mDelayCyclesPerUs = (SYS_CLK_HZ / 1000000 / NOP_FOR_LOOP_INSTRUCTION_COUNT);
  176. /* Enable RTC clock and oscillator */
  177. SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
  178. if (RTC->SR & RTC_SR_TIF_MASK) {
  179. /* Resets the RTC registers except for the SWR bit */
  180. RTC->CR |= RTC_CR_SWR_MASK;
  181. RTC->CR &= ~RTC_CR_SWR_MASK;
  182. /* Set TSR register to 0x1 to avoid the TIF bit being set in the SR register */
  183. RTC->TSR = 1;
  184. }
  185. /* Disable RTC Interrupts */
  186. RTC->IER = 0;
  187. /* Enable OSC */
  188. if ((RTC->CR & RTC_CR_OSCE_MASK) == 0) {
  189. /* Turn on */
  190. RTC->CR |= RTC_CR_OSCE_MASK;
  191. /* Wait RTC startup delay 1000 us */
  192. delay_us(1000);
  193. }
  194. /* Enable counter */
  195. RTC->SR |= RTC_SR_TCE_MASK;
  196. }
  197. static void hw_rand_init(void)
  198. {
  199. #ifdef FREESCALE_KSDK_BM
  200. trng_config_t trngConfig;
  201. TRNG_GetDefaultConfig(&trngConfig);
  202. /* Set sample mode of the TRNG ring oscillator to Von Neumann, for better random data.*/
  203. trngConfig.sampleMode = kTRNG_SampleModeVonNeumann;
  204. /* Initialize TRNG */
  205. TRNG_Init(TRNG0, &trngConfig);
  206. #else
  207. /* Enable RNG clocks */
  208. SIM->SCGC6 |= SIM_SCGC6_RNGA_MASK;
  209. SIM->SCGC3 |= SIM_SCGC3_RNGA_MASK;
  210. /* Wake up RNG to normal mode (take out of sleep) */
  211. RNG->CR &= ~RNG_CR_SLP_MASK;
  212. /* Enable High Assurance mode (Enables notification of security violations via SR[SECV]) */
  213. RNG->CR |= RNG_CR_HA_MASK;
  214. /* Enable RNG generation to RANDOUT FIFO */
  215. RNG->CR |= RNG_CR_GO_MASK;
  216. #endif
  217. }
  218. /* Public Functions */
  219. void hw_init(void)
  220. {
  221. hw_mcg_init();
  222. hw_gpio_init();
  223. hw_uart_init();
  224. hw_rtc_init();
  225. hw_rand_init();
  226. }
  227. uint32_t hw_get_time_sec(void)
  228. {
  229. /* Return RTC seconds */
  230. return RTC->TSR;
  231. }
  232. uint32_t hw_get_time_msec(void)
  233. {
  234. /* RTC TPR precision register increments every 32.768 kHz clock cycle */
  235. /* Convert with rounding crystal count (32768 or (1 << 15)) to milliseconds */
  236. return ( ((uint32_t)RTC->TPR * 1000) + ((1 << 15) / 2) ) / (1 << 15);
  237. }
  238. void hw_uart_printchar(int c)
  239. {
  240. #ifdef FREESCALE_KSDK_BM
  241. LPUART_WriteBlocking(UART_PORT, (const uint8_t*)&c, 1); /* Send the character */
  242. #else
  243. while(!(UART_PORT->S1 & UART_S1_TDRE_MASK)); /* Wait until space is available in the FIFO */
  244. UART_PORT->D = (uint8_t)c; /* Send the character */
  245. #endif
  246. }
  247. uint32_t hw_rand(void)
  248. {
  249. uint32_t rng;
  250. #ifdef FREESCALE_KSDK_BM
  251. TRNG_GetRandomData(TRNG0, &rng, sizeof(rng));
  252. #else
  253. while((RNG->SR & RNG_SR_OREG_LVL(0xF)) == 0) {}; /* Wait until FIFO has a value available */
  254. rng = RNG->OR; /* Return next value in FIFO output register */
  255. #endif
  256. return rng;
  257. }
  258. void delay_us(uint32_t microseconds)
  259. {
  260. delay_nop(mDelayCyclesPerUs * microseconds);
  261. }
  262. // Watchdog
  263. void hw_watchdog_disable(void)
  264. {
  265. WDOG->UNLOCK = 0xC520;
  266. WDOG->UNLOCK = 0xD928;
  267. WDOG->STCTRLH = WDOG_STCTRLH_ALLOWUPDATE_MASK;
  268. }
  269. // Flash configuration
  270. #define FSEC_UNSECURE 2
  271. #define FSEC_SECURE 0
  272. #define FSEC_FSLACC_DENIED 2
  273. #define FSEC_FSLACC_GRANTED 3
  274. #define FSEC_KEY_ENABLED 2
  275. #define FSEC_KEY_DISABLED 3
  276. #define FSEC_MASS_ERASE_DISABLE 2
  277. #define FSEC_MASS_ERASE_ENABLE 3
  278. struct flash_conf {
  279. uint8_t backdoor_key[8]; /* Backdoor Comparison Key */
  280. uint8_t fprot[4]; /* Program flash protection bytes */
  281. uint8_t fsec; /* Flash security byte */
  282. uint8_t fopt; /* Flash nonvolatile option byte */
  283. uint8_t feprot; /* FlexNVM: EEPROM protection byte */
  284. uint8_t fdprot; /* FlexNVM: Data flash protection byte */
  285. };
  286. const struct flash_conf flash_conf __attribute__ ((section (".flashconf"),used)) =
  287. {
  288. .backdoor_key = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
  289. .fprot = { 0xFF, 0xFF, 0xFF, 0xFF },
  290. .fsec = NV_FSEC_SEC(FSEC_UNSECURE) | NV_FSEC_FSLACC(FSEC_FSLACC_GRANTED) |
  291. NV_FSEC_MEEN(FSEC_MASS_ERASE_ENABLE) | NV_FSEC_KEYEN(FSEC_KEY_DISABLED),
  292. .fopt = 0xFF,
  293. .feprot = 0xFF,
  294. .fdprot = 0xFF
  295. };
  296. #endif /* FREESCALE && K_SERIES */