spi-rb4xx.c 9.7 KB

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  1. /*
  2. * SPI controller driver for the Mikrotik RB4xx boards
  3. *
  4. * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  5. *
  6. * This file was based on the patches for Linux 2.6.27.39 published by
  7. * MikroTik for their RouterBoard 4xx series devices.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/err.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/init.h>
  19. #include <linux/delay.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/workqueue.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/spi/spi.h>
  24. #include <asm/mach-ath79/ar71xx_regs.h>
  25. #include <asm/mach-ath79/ath79.h>
  26. #define DRV_NAME "rb4xx-spi"
  27. #define DRV_DESC "Mikrotik RB4xx SPI controller driver"
  28. #define DRV_VERSION "0.1.0"
  29. #define SPI_CTRL_FASTEST 0x40
  30. #define SPI_FLASH_HZ 33333334
  31. #define SPI_CPLD_HZ 33333334
  32. #define CPLD_CMD_READ_FAST 0x0b
  33. #undef RB4XX_SPI_DEBUG
  34. struct rb4xx_spi {
  35. void __iomem *base;
  36. struct spi_master *master;
  37. unsigned spi_ctrl_flash;
  38. unsigned spi_ctrl_fread;
  39. struct clk *ahb_clk;
  40. unsigned long ahb_freq;
  41. spinlock_t lock;
  42. struct list_head queue;
  43. int busy:1;
  44. int cs_wait;
  45. };
  46. static unsigned spi_clk_low = AR71XX_SPI_IOC_CS1;
  47. #ifdef RB4XX_SPI_DEBUG
  48. static inline void do_spi_delay(void)
  49. {
  50. ndelay(20000);
  51. }
  52. #else
  53. static inline void do_spi_delay(void) { }
  54. #endif
  55. static inline void do_spi_init(struct spi_device *spi)
  56. {
  57. unsigned cs = AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1;
  58. if (!(spi->mode & SPI_CS_HIGH))
  59. cs ^= (spi->chip_select == 2) ? AR71XX_SPI_IOC_CS1 :
  60. AR71XX_SPI_IOC_CS0;
  61. spi_clk_low = cs;
  62. }
  63. static inline void do_spi_finish(void __iomem *base)
  64. {
  65. do_spi_delay();
  66. __raw_writel(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1,
  67. base + AR71XX_SPI_REG_IOC);
  68. }
  69. static inline void do_spi_clk(void __iomem *base, int bit)
  70. {
  71. unsigned bval = spi_clk_low | ((bit & 1) ? AR71XX_SPI_IOC_DO : 0);
  72. do_spi_delay();
  73. __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
  74. do_spi_delay();
  75. __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
  76. }
  77. static void do_spi_byte(void __iomem *base, unsigned char byte)
  78. {
  79. do_spi_clk(base, byte >> 7);
  80. do_spi_clk(base, byte >> 6);
  81. do_spi_clk(base, byte >> 5);
  82. do_spi_clk(base, byte >> 4);
  83. do_spi_clk(base, byte >> 3);
  84. do_spi_clk(base, byte >> 2);
  85. do_spi_clk(base, byte >> 1);
  86. do_spi_clk(base, byte);
  87. pr_debug("spi_byte sent 0x%02x got 0x%02x\n",
  88. (unsigned)byte,
  89. (unsigned char)__raw_readl(base + AR71XX_SPI_REG_RDS));
  90. }
  91. static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1,
  92. unsigned bit2)
  93. {
  94. unsigned bval = (spi_clk_low |
  95. ((bit1 & 1) ? AR71XX_SPI_IOC_DO : 0) |
  96. ((bit2 & 1) ? AR71XX_SPI_IOC_CS2 : 0));
  97. do_spi_delay();
  98. __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
  99. do_spi_delay();
  100. __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
  101. }
  102. static void do_spi_byte_fast(void __iomem *base, unsigned char byte)
  103. {
  104. do_spi_clk_fast(base, byte >> 7, byte >> 6);
  105. do_spi_clk_fast(base, byte >> 5, byte >> 4);
  106. do_spi_clk_fast(base, byte >> 3, byte >> 2);
  107. do_spi_clk_fast(base, byte >> 1, byte >> 0);
  108. pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n",
  109. (unsigned)byte,
  110. (unsigned char) __raw_readl(base + AR71XX_SPI_REG_RDS));
  111. }
  112. static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t)
  113. {
  114. const unsigned char *tx_ptr = t->tx_buf;
  115. unsigned char *rx_ptr = t->rx_buf;
  116. unsigned i;
  117. pr_debug("spi_txrx len %u tx %u rx %u\n",
  118. t->len,
  119. (t->tx_buf ? 1 : 0),
  120. (t->rx_buf ? 1 : 0));
  121. for (i = 0; i < t->len; ++i) {
  122. unsigned char sdata = tx_ptr ? tx_ptr[i] : 0;
  123. if (t->tx_nbits == SPI_NBITS_DUAL)
  124. do_spi_byte_fast(base, sdata);
  125. else
  126. do_spi_byte(base, sdata);
  127. if (rx_ptr)
  128. rx_ptr[i] = __raw_readl(base + AR71XX_SPI_REG_RDS) & 0xff;
  129. }
  130. return i;
  131. }
  132. static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m)
  133. {
  134. struct spi_transfer *t = NULL;
  135. void __iomem *base = rbspi->base;
  136. m->status = 0;
  137. if (list_empty(&m->transfers))
  138. return -1;
  139. __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
  140. __raw_writel(SPI_CTRL_FASTEST, base + AR71XX_SPI_REG_CTRL);
  141. do_spi_init(m->spi);
  142. list_for_each_entry(t, &m->transfers, transfer_list) {
  143. int len;
  144. len = rb4xx_spi_txrx(base, t);
  145. if (len != t->len) {
  146. m->status = -EMSGSIZE;
  147. break;
  148. }
  149. m->actual_length += len;
  150. if (t->cs_change) {
  151. if (list_is_last(&t->transfer_list, &m->transfers)) {
  152. /* wait for continuation */
  153. return m->spi->chip_select;
  154. }
  155. do_spi_finish(base);
  156. ndelay(100);
  157. }
  158. }
  159. do_spi_finish(base);
  160. __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
  161. __raw_writel(0, base + AR71XX_SPI_REG_FS);
  162. return -1;
  163. }
  164. static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi,
  165. unsigned long *flags)
  166. {
  167. int cs = rbspi->cs_wait;
  168. rbspi->busy = 1;
  169. while (!list_empty(&rbspi->queue)) {
  170. struct spi_message *m;
  171. list_for_each_entry(m, &rbspi->queue, queue)
  172. if (cs < 0 || cs == m->spi->chip_select)
  173. break;
  174. if (&m->queue == &rbspi->queue)
  175. break;
  176. list_del_init(&m->queue);
  177. spin_unlock_irqrestore(&rbspi->lock, *flags);
  178. cs = rb4xx_spi_msg(rbspi, m);
  179. m->complete(m->context);
  180. spin_lock_irqsave(&rbspi->lock, *flags);
  181. }
  182. rbspi->cs_wait = cs;
  183. rbspi->busy = 0;
  184. if (cs >= 0) {
  185. /* TODO: add timer to unlock cs after 1s inactivity */
  186. }
  187. }
  188. static int rb4xx_spi_transfer(struct spi_device *spi,
  189. struct spi_message *m)
  190. {
  191. struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
  192. unsigned long flags;
  193. m->actual_length = 0;
  194. m->status = -EINPROGRESS;
  195. spin_lock_irqsave(&rbspi->lock, flags);
  196. list_add_tail(&m->queue, &rbspi->queue);
  197. if (rbspi->busy ||
  198. (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) {
  199. /* job will be done later */
  200. spin_unlock_irqrestore(&rbspi->lock, flags);
  201. return 0;
  202. }
  203. /* process job in current context */
  204. rb4xx_spi_process_queue_locked(rbspi, &flags);
  205. spin_unlock_irqrestore(&rbspi->lock, flags);
  206. return 0;
  207. }
  208. static int rb4xx_spi_setup(struct spi_device *spi)
  209. {
  210. struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
  211. unsigned long flags;
  212. if (spi->mode & ~(SPI_CS_HIGH | SPI_TX_DUAL)) {
  213. dev_err(&spi->dev, "mode %x not supported\n",
  214. (unsigned) spi->mode);
  215. return -EINVAL;
  216. }
  217. if (spi->bits_per_word != 8 && spi->bits_per_word != 0) {
  218. dev_err(&spi->dev, "bits_per_word %u not supported\n",
  219. (unsigned) spi->bits_per_word);
  220. return -EINVAL;
  221. }
  222. spin_lock_irqsave(&rbspi->lock, flags);
  223. if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) {
  224. rbspi->cs_wait = -1;
  225. rb4xx_spi_process_queue_locked(rbspi, &flags);
  226. }
  227. spin_unlock_irqrestore(&rbspi->lock, flags);
  228. return 0;
  229. }
  230. static unsigned get_spi_ctrl(struct rb4xx_spi *rbspi, unsigned hz_max,
  231. const char *name)
  232. {
  233. unsigned div;
  234. div = (rbspi->ahb_freq - 1) / (2 * hz_max);
  235. /*
  236. * CPU has a bug at (div == 0) - first bit read is random
  237. */
  238. if (div == 0)
  239. ++div;
  240. if (name) {
  241. unsigned ahb_khz = (rbspi->ahb_freq + 500) / 1000;
  242. unsigned div_real = 2 * (div + 1);
  243. pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n",
  244. name,
  245. ahb_khz / div_real,
  246. ahb_khz, div_real);
  247. }
  248. return SPI_CTRL_FASTEST + div;
  249. }
  250. static int rb4xx_spi_probe(struct platform_device *pdev)
  251. {
  252. struct spi_master *master;
  253. struct rb4xx_spi *rbspi;
  254. struct resource *r;
  255. int err = 0;
  256. master = spi_alloc_master(&pdev->dev, sizeof(*rbspi));
  257. if (master == NULL) {
  258. dev_err(&pdev->dev, "no memory for spi_master\n");
  259. err = -ENOMEM;
  260. goto err_out;
  261. }
  262. master->bus_num = 0;
  263. master->num_chipselect = 3;
  264. master->mode_bits = SPI_TX_DUAL;
  265. master->setup = rb4xx_spi_setup;
  266. master->transfer = rb4xx_spi_transfer;
  267. rbspi = spi_master_get_devdata(master);
  268. rbspi->ahb_clk = clk_get(&pdev->dev, "ahb");
  269. if (IS_ERR(rbspi->ahb_clk)) {
  270. err = PTR_ERR(rbspi->ahb_clk);
  271. goto err_put_master;
  272. }
  273. err = clk_prepare_enable(rbspi->ahb_clk);
  274. if (err)
  275. goto err_clk_put;
  276. rbspi->ahb_freq = clk_get_rate(rbspi->ahb_clk);
  277. if (!rbspi->ahb_freq) {
  278. err = -EINVAL;
  279. goto err_clk_disable;
  280. }
  281. platform_set_drvdata(pdev, rbspi);
  282. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  283. if (r == NULL) {
  284. err = -ENOENT;
  285. goto err_clk_disable;
  286. }
  287. rbspi->base = ioremap(r->start, r->end - r->start + 1);
  288. if (!rbspi->base) {
  289. err = -ENXIO;
  290. goto err_clk_disable;
  291. }
  292. rbspi->master = master;
  293. rbspi->spi_ctrl_flash = get_spi_ctrl(rbspi, SPI_FLASH_HZ, "FLASH");
  294. rbspi->spi_ctrl_fread = get_spi_ctrl(rbspi, SPI_CPLD_HZ, "CPLD");
  295. rbspi->cs_wait = -1;
  296. spin_lock_init(&rbspi->lock);
  297. INIT_LIST_HEAD(&rbspi->queue);
  298. err = spi_register_master(master);
  299. if (err) {
  300. dev_err(&pdev->dev, "failed to register SPI master\n");
  301. goto err_iounmap;
  302. }
  303. return 0;
  304. err_iounmap:
  305. iounmap(rbspi->base);
  306. err_clk_disable:
  307. clk_disable(rbspi->ahb_clk);
  308. err_clk_put:
  309. clk_put(rbspi->ahb_clk);
  310. err_put_master:
  311. platform_set_drvdata(pdev, NULL);
  312. spi_master_put(master);
  313. err_out:
  314. return err;
  315. }
  316. static int rb4xx_spi_remove(struct platform_device *pdev)
  317. {
  318. struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
  319. iounmap(rbspi->base);
  320. clk_disable(rbspi->ahb_clk);
  321. clk_put(rbspi->ahb_clk);
  322. platform_set_drvdata(pdev, NULL);
  323. spi_master_put(rbspi->master);
  324. return 0;
  325. }
  326. static struct platform_driver rb4xx_spi_drv = {
  327. .probe = rb4xx_spi_probe,
  328. .remove = rb4xx_spi_remove,
  329. .driver = {
  330. .name = DRV_NAME,
  331. .owner = THIS_MODULE,
  332. },
  333. };
  334. static int __init rb4xx_spi_init(void)
  335. {
  336. return platform_driver_register(&rb4xx_spi_drv);
  337. }
  338. subsys_initcall(rb4xx_spi_init);
  339. static void __exit rb4xx_spi_exit(void)
  340. {
  341. platform_driver_unregister(&rb4xx_spi_drv);
  342. }
  343. module_exit(rb4xx_spi_exit);
  344. MODULE_DESCRIPTION(DRV_DESC);
  345. MODULE_VERSION(DRV_VERSION);
  346. MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  347. MODULE_LICENSE("GPL v2");