1
0

0042-SPI-ralink-add-Ralink-SoC-spi-driver.patch 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574
  1. From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Sun, 27 Jul 2014 11:15:12 +0100
  4. Subject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver
  5. Add the driver needed to make SPI work on Ralink SoC.
  6. Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  7. Acked-by: John Crispin <blogic@openwrt.org>
  8. ---
  9. drivers/spi/Kconfig | 6 +
  10. drivers/spi/Makefile | 1 +
  11. drivers/spi/spi-rt2880.c | 530 ++++++++++++++++++++++++++++++++++++++++++++++
  12. 3 files changed, 537 insertions(+)
  13. create mode 100644 drivers/spi/spi-rt2880.c
  14. --- a/drivers/spi/Kconfig
  15. +++ b/drivers/spi/Kconfig
  16. @@ -477,6 +477,12 @@ config SPI_QUP
  17. This driver can also be built as a module. If so, the module
  18. will be called spi_qup.
  19. +config SPI_RT2880
  20. + tristate "Ralink RT288x SPI Controller"
  21. + depends on RALINK
  22. + help
  23. + This selects a driver for the Ralink RT288x/RT305x SPI Controller.
  24. +
  25. config SPI_S3C24XX
  26. tristate "Samsung S3C24XX series SPI"
  27. depends on ARCH_S3C24XX
  28. --- a/drivers/spi/Makefile
  29. +++ b/drivers/spi/Makefile
  30. @@ -70,6 +70,7 @@ obj-$(CONFIG_SPI_QUP) += spi-qup.o
  31. obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
  32. obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
  33. obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
  34. +obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o
  35. obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
  36. spi-s3c24xx-hw-y := spi-s3c24xx.o
  37. spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
  38. --- /dev/null
  39. +++ b/drivers/spi/spi-rt2880.c
  40. @@ -0,0 +1,530 @@
  41. +/*
  42. + * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
  43. + *
  44. + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  45. + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  46. + *
  47. + * Some parts are based on spi-orion.c:
  48. + * Author: Shadi Ammouri <shadi@marvell.com>
  49. + * Copyright (C) 2007-2008 Marvell Ltd.
  50. + *
  51. + * This program is free software; you can redistribute it and/or modify
  52. + * it under the terms of the GNU General Public License version 2 as
  53. + * published by the Free Software Foundation.
  54. + */
  55. +
  56. +#include <linux/init.h>
  57. +#include <linux/module.h>
  58. +#include <linux/clk.h>
  59. +#include <linux/err.h>
  60. +#include <linux/delay.h>
  61. +#include <linux/io.h>
  62. +#include <linux/reset.h>
  63. +#include <linux/spi/spi.h>
  64. +#include <linux/platform_device.h>
  65. +#include <linux/gpio.h>
  66. +
  67. +#define DRIVER_NAME "spi-rt2880"
  68. +
  69. +#define RAMIPS_SPI_STAT 0x00
  70. +#define RAMIPS_SPI_CFG 0x10
  71. +#define RAMIPS_SPI_CTL 0x14
  72. +#define RAMIPS_SPI_DATA 0x20
  73. +#define RAMIPS_SPI_ADDR 0x24
  74. +#define RAMIPS_SPI_BS 0x28
  75. +#define RAMIPS_SPI_USER 0x2C
  76. +#define RAMIPS_SPI_TXFIFO 0x30
  77. +#define RAMIPS_SPI_RXFIFO 0x34
  78. +#define RAMIPS_SPI_FIFO_STAT 0x38
  79. +#define RAMIPS_SPI_MODE 0x3C
  80. +#define RAMIPS_SPI_DEV_OFFSET 0x40
  81. +#define RAMIPS_SPI_DMA 0x80
  82. +#define RAMIPS_SPI_DMASTAT 0x84
  83. +#define RAMIPS_SPI_ARBITER 0xF0
  84. +
  85. +/* SPISTAT register bit field */
  86. +#define SPISTAT_BUSY BIT(0)
  87. +
  88. +/* SPICFG register bit field */
  89. +#define SPICFG_ADDRMODE BIT(12)
  90. +#define SPICFG_RXENVDIS BIT(11)
  91. +#define SPICFG_RXCAP BIT(10)
  92. +#define SPICFG_SPIENMODE BIT(9)
  93. +#define SPICFG_MSBFIRST BIT(8)
  94. +#define SPICFG_SPICLKPOL BIT(6)
  95. +#define SPICFG_RXCLKEDGE_FALLING BIT(5)
  96. +#define SPICFG_TXCLKEDGE_FALLING BIT(4)
  97. +#define SPICFG_HIZSPI BIT(3)
  98. +#define SPICFG_SPICLK_PRESCALE_MASK 0x7
  99. +#define SPICFG_SPICLK_DIV2 0
  100. +#define SPICFG_SPICLK_DIV4 1
  101. +#define SPICFG_SPICLK_DIV8 2
  102. +#define SPICFG_SPICLK_DIV16 3
  103. +#define SPICFG_SPICLK_DIV32 4
  104. +#define SPICFG_SPICLK_DIV64 5
  105. +#define SPICFG_SPICLK_DIV128 6
  106. +#define SPICFG_SPICLK_DISABLE 7
  107. +
  108. +/* SPICTL register bit field */
  109. +#define SPICTL_START BIT(4)
  110. +#define SPICTL_HIZSDO BIT(3)
  111. +#define SPICTL_STARTWR BIT(2)
  112. +#define SPICTL_STARTRD BIT(1)
  113. +#define SPICTL_SPIENA BIT(0)
  114. +
  115. +/* SPIUSER register bit field */
  116. +#define SPIUSER_USERMODE BIT(21)
  117. +#define SPIUSER_INSTR_PHASE BIT(20)
  118. +#define SPIUSER_ADDR_PHASE_MASK 0x7
  119. +#define SPIUSER_ADDR_PHASE_OFFSET 17
  120. +#define SPIUSER_MODE_PHASE BIT(16)
  121. +#define SPIUSER_DUMMY_PHASE_MASK 0x3
  122. +#define SPIUSER_DUMMY_PHASE_OFFSET 14
  123. +#define SPIUSER_DATA_PHASE_MASK 0x3
  124. +#define SPIUSER_DATA_PHASE_OFFSET 12
  125. +#define SPIUSER_DATA_READ (BIT(0) << SPIUSER_DATA_PHASE_OFFSET)
  126. +#define SPIUSER_DATA_WRITE (BIT(1) << SPIUSER_DATA_PHASE_OFFSET)
  127. +#define SPIUSER_ADDR_TYPE_OFFSET 9
  128. +#define SPIUSER_MODE_TYPE_OFFSET 6
  129. +#define SPIUSER_DUMMY_TYPE_OFFSET 3
  130. +#define SPIUSER_DATA_TYPE_OFFSET 0
  131. +#define SPIUSER_TRANSFER_MASK 0x7
  132. +#define SPIUSER_TRANSFER_SINGLE BIT(0)
  133. +#define SPIUSER_TRANSFER_DUAL BIT(1)
  134. +#define SPIUSER_TRANSFER_QUAD BIT(2)
  135. +
  136. +#define SPIUSER_TRANSFER_TYPE(type) ( \
  137. + (type << SPIUSER_ADDR_TYPE_OFFSET) | \
  138. + (type << SPIUSER_MODE_TYPE_OFFSET) | \
  139. + (type << SPIUSER_DUMMY_TYPE_OFFSET) | \
  140. + (type << SPIUSER_DATA_TYPE_OFFSET) \
  141. +)
  142. +
  143. +/* SPIFIFOSTAT register bit field */
  144. +#define SPIFIFOSTAT_TXEMPTY BIT(19)
  145. +#define SPIFIFOSTAT_RXEMPTY BIT(18)
  146. +#define SPIFIFOSTAT_TXFULL BIT(17)
  147. +#define SPIFIFOSTAT_RXFULL BIT(16)
  148. +#define SPIFIFOSTAT_FIFO_MASK 0xff
  149. +#define SPIFIFOSTAT_TX_OFFSET 8
  150. +#define SPIFIFOSTAT_RX_OFFSET 0
  151. +
  152. +#define SPI_FIFO_DEPTH 16
  153. +
  154. +/* SPIMODE register bit field */
  155. +#define SPIMODE_MODE_OFFSET 24
  156. +#define SPIMODE_DUMMY_OFFSET 0
  157. +
  158. +/* SPIARB register bit field */
  159. +#define SPICTL_ARB_EN BIT(31)
  160. +#define SPICTL_CSCTL1 BIT(16)
  161. +#define SPI1_POR BIT(1)
  162. +#define SPI0_POR BIT(0)
  163. +
  164. +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \
  165. + SPI_CS_HIGH)
  166. +
  167. +static atomic_t hw_reset_count = ATOMIC_INIT(0);
  168. +
  169. +struct rt2880_spi {
  170. + struct spi_master *master;
  171. + void __iomem *base;
  172. + u32 speed;
  173. + u16 wait_loops;
  174. + u16 mode;
  175. + struct clk *clk;
  176. +};
  177. +
  178. +static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
  179. +{
  180. + return spi_master_get_devdata(spi->master);
  181. +}
  182. +
  183. +static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
  184. +{
  185. + return ioread32(rs->base + reg);
  186. +}
  187. +
  188. +static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg,
  189. + const u32 val)
  190. +{
  191. + iowrite32(val, rs->base + reg);
  192. +}
  193. +
  194. +static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
  195. +{
  196. + void __iomem *addr = rs->base + reg;
  197. +
  198. + iowrite32((ioread32(addr) | mask), addr);
  199. +}
  200. +
  201. +static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
  202. +{
  203. + void __iomem *addr = rs->base + reg;
  204. +
  205. + iowrite32((ioread32(addr) & ~mask), addr);
  206. +}
  207. +
  208. +static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed)
  209. +{
  210. + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
  211. + u32 rate;
  212. + u32 prescale;
  213. +
  214. + /*
  215. + * the supported rates are: 2, 4, 8, ... 128
  216. + * round up as we look for equal or less speed
  217. + */
  218. + rate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed);
  219. + rate = roundup_pow_of_two(rate);
  220. +
  221. + /* Convert the rate to SPI clock divisor value. */
  222. + prescale = ilog2(rate / 2);
  223. +
  224. + /* some tolerance. double and add 100 */
  225. + rs->wait_loops = (8 * HZ * loops_per_jiffy) /
  226. + (clk_get_rate(rs->clk) / rate);
  227. + rs->wait_loops = (rs->wait_loops << 1) + 100;
  228. + rs->speed = speed;
  229. +
  230. + dev_dbg(&spi->dev, "speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\n",
  231. + clk_get_rate(rs->clk) / rate, speed, rate, prescale,
  232. + rs->wait_loops);
  233. +
  234. + return prescale;
  235. +}
  236. +
  237. +static u32 get_arbiter_offset(struct spi_master *master)
  238. +{
  239. + u32 offset;
  240. +
  241. + offset = RAMIPS_SPI_ARBITER;
  242. + if (master->bus_num == 1)
  243. + offset -= RAMIPS_SPI_DEV_OFFSET;
  244. +
  245. + return offset;
  246. +}
  247. +
  248. +static void rt2880_spi_set_cs(struct spi_device *spi, bool enable)
  249. +{
  250. + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
  251. +
  252. + if (enable)
  253. + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
  254. + else
  255. + rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
  256. +}
  257. +
  258. +static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len)
  259. +{
  260. + int loop = rs->wait_loops * len;
  261. +
  262. + while ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop)
  263. + cpu_relax();
  264. +
  265. + if (loop)
  266. + return 0;
  267. +
  268. + return -ETIMEDOUT;
  269. +}
  270. +
  271. +static void rt2880_dump_reg(struct spi_master *master)
  272. +{
  273. + struct rt2880_spi *rs = spi_master_get_devdata(master);
  274. +
  275. + dev_dbg(&master->dev, "stat: %08x, cfg: %08x, ctl: %08x, " \
  276. + "data: %08x, arb: %08x\n",
  277. + rt2880_spi_read(rs, RAMIPS_SPI_STAT),
  278. + rt2880_spi_read(rs, RAMIPS_SPI_CFG),
  279. + rt2880_spi_read(rs, RAMIPS_SPI_CTL),
  280. + rt2880_spi_read(rs, RAMIPS_SPI_DATA),
  281. + rt2880_spi_read(rs, get_arbiter_offset(master)));
  282. +}
  283. +
  284. +static int rt2880_spi_transfer_one(struct spi_master *master,
  285. + struct spi_device *spi, struct spi_transfer *xfer)
  286. +{
  287. + struct rt2880_spi *rs = spi_master_get_devdata(master);
  288. + unsigned len;
  289. + const u8 *tx = xfer->tx_buf;
  290. + u8 *rx = xfer->rx_buf;
  291. + int err = 0;
  292. +
  293. + /* change clock speed */
  294. + if (unlikely(rs->speed != xfer->speed_hz)) {
  295. + u32 reg;
  296. + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
  297. + reg &= ~SPICFG_SPICLK_PRESCALE_MASK;
  298. + reg |= rt2880_spi_baudrate_get(spi, xfer->speed_hz);
  299. + rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
  300. + }
  301. +
  302. + if (tx) {
  303. + len = xfer->len;
  304. + while (len-- > 0) {
  305. + rt2880_spi_write(rs, RAMIPS_SPI_DATA, *tx++);
  306. + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
  307. + err = rt2880_spi_wait_ready(rs, 1);
  308. + if (err) {
  309. + dev_err(&spi->dev, "TX failed, err=%d\n", err);
  310. + goto out;
  311. + }
  312. + }
  313. + }
  314. +
  315. + if (rx) {
  316. + len = xfer->len;
  317. + while (len-- > 0) {
  318. + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
  319. + err = rt2880_spi_wait_ready(rs, 1);
  320. + if (err) {
  321. + dev_err(&spi->dev, "RX failed, err=%d\n", err);
  322. + goto out;
  323. + }
  324. + *rx++ = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
  325. + }
  326. + }
  327. +
  328. +out:
  329. + return err;
  330. +}
  331. +
  332. +/* copy from spi.c */
  333. +static void spi_set_cs(struct spi_device *spi, bool enable)
  334. +{
  335. + if (spi->mode & SPI_CS_HIGH)
  336. + enable = !enable;
  337. +
  338. + if (spi->cs_gpio >= 0)
  339. + gpio_set_value(spi->cs_gpio, !enable);
  340. + else if (spi->master->set_cs)
  341. + spi->master->set_cs(spi, !enable);
  342. +}
  343. +
  344. +static int rt2880_spi_setup(struct spi_device *spi)
  345. +{
  346. + struct spi_master *master = spi->master;
  347. + struct rt2880_spi *rs = spi_master_get_devdata(master);
  348. + u32 reg, old_reg, arbit_off;
  349. +
  350. + if ((spi->max_speed_hz > master->max_speed_hz) ||
  351. + (spi->max_speed_hz < master->min_speed_hz)) {
  352. + dev_err(&spi->dev, "invalide requested speed %d Hz\n",
  353. + spi->max_speed_hz);
  354. + return -EINVAL;
  355. + }
  356. +
  357. + if (!(master->bits_per_word_mask &
  358. + BIT(spi->bits_per_word - 1))) {
  359. + dev_err(&spi->dev, "invalide bits_per_word %d\n",
  360. + spi->bits_per_word);
  361. + return -EINVAL;
  362. + }
  363. +
  364. + /* the hardware seems can't work on mode0 force it to mode3 */
  365. + if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) {
  366. + dev_warn(&spi->dev, "force spi mode3\n");
  367. + spi->mode |= SPI_MODE_3;
  368. + }
  369. +
  370. + /* chip polarity */
  371. + arbit_off = get_arbiter_offset(master);
  372. + reg = old_reg = rt2880_spi_read(rs, arbit_off);
  373. + if (spi->mode & SPI_CS_HIGH) {
  374. + switch (master->bus_num) {
  375. + case 1:
  376. + reg |= SPI1_POR;
  377. + break;
  378. + default:
  379. + reg |= SPI0_POR;
  380. + break;
  381. + }
  382. + } else {
  383. + switch (master->bus_num) {
  384. + case 1:
  385. + reg &= ~SPI1_POR;
  386. + break;
  387. + default:
  388. + reg &= ~SPI0_POR;
  389. + break;
  390. + }
  391. + }
  392. +
  393. + /* enable spi1 */
  394. + if (master->bus_num == 1)
  395. + reg |= SPICTL_ARB_EN;
  396. +
  397. + if (reg != old_reg)
  398. + rt2880_spi_write(rs, arbit_off, reg);
  399. +
  400. + /* deselected the spi device */
  401. + spi_set_cs(spi, false);
  402. +
  403. + rt2880_dump_reg(master);
  404. +
  405. + return 0;
  406. +}
  407. +
  408. +static int rt2880_spi_prepare_message(struct spi_master *master,
  409. + struct spi_message *msg)
  410. +{
  411. + struct rt2880_spi *rs = spi_master_get_devdata(master);
  412. + struct spi_device *spi = msg->spi;
  413. + u32 reg;
  414. +
  415. + if ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz))
  416. + return 0;
  417. +
  418. +#if 0
  419. + /* set spido to tri-state */
  420. + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO);
  421. +#endif
  422. +
  423. + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
  424. +
  425. + reg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL |
  426. + SPICFG_RXCLKEDGE_FALLING |
  427. + SPICFG_TXCLKEDGE_FALLING |
  428. + SPICFG_SPICLK_PRESCALE_MASK);
  429. +
  430. + /* MSB */
  431. + if (!(spi->mode & SPI_LSB_FIRST))
  432. + reg |= SPICFG_MSBFIRST;
  433. +
  434. + /* spi mode */
  435. + switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
  436. + case SPI_MODE_0:
  437. + reg |= SPICFG_TXCLKEDGE_FALLING;
  438. + break;
  439. + case SPI_MODE_1:
  440. + reg |= SPICFG_RXCLKEDGE_FALLING;
  441. + break;
  442. + case SPI_MODE_2:
  443. + reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;
  444. + break;
  445. + case SPI_MODE_3:
  446. + reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;
  447. + break;
  448. + }
  449. + rs->mode = spi->mode;
  450. +
  451. +#if 0
  452. + /* set spiclk and spiena to tri-state */
  453. + reg |= SPICFG_HIZSPI;
  454. +#endif
  455. +
  456. + /* clock divide */
  457. + reg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz);
  458. +
  459. + rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
  460. +
  461. + return 0;
  462. +}
  463. +
  464. +static int rt2880_spi_probe(struct platform_device *pdev)
  465. +{
  466. + struct spi_master *master;
  467. + struct rt2880_spi *rs;
  468. + void __iomem *base;
  469. + struct resource *r;
  470. + struct clk *clk;
  471. + int ret;
  472. +
  473. + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  474. + base = devm_ioremap_resource(&pdev->dev, r);
  475. + if (IS_ERR(base))
  476. + return PTR_ERR(base);
  477. +
  478. + clk = devm_clk_get(&pdev->dev, NULL);
  479. + if (IS_ERR(clk)) {
  480. + dev_err(&pdev->dev, "unable to get SYS clock\n");
  481. + return PTR_ERR(clk);
  482. + }
  483. +
  484. + ret = clk_prepare_enable(clk);
  485. + if (ret)
  486. + goto err_clk;
  487. +
  488. + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
  489. + if (master == NULL) {
  490. + dev_dbg(&pdev->dev, "master allocation failed\n");
  491. + ret = -ENOMEM;
  492. + goto err_clk;
  493. + }
  494. +
  495. + master->dev.of_node = pdev->dev.of_node;
  496. + master->mode_bits = RT2880_SPI_MODE_BITS;
  497. + master->bits_per_word_mask = SPI_BPW_MASK(8);
  498. + master->min_speed_hz = clk_get_rate(clk) / 128;
  499. + master->max_speed_hz = clk_get_rate(clk) / 2;
  500. + master->flags = SPI_MASTER_HALF_DUPLEX;
  501. + master->setup = rt2880_spi_setup;
  502. + master->prepare_message = rt2880_spi_prepare_message;
  503. + master->set_cs = rt2880_spi_set_cs;
  504. + master->transfer_one = rt2880_spi_transfer_one,
  505. +
  506. + dev_set_drvdata(&pdev->dev, master);
  507. +
  508. + rs = spi_master_get_devdata(master);
  509. + rs->master = master;
  510. + rs->base = base;
  511. + rs->clk = clk;
  512. +
  513. + if (atomic_inc_return(&hw_reset_count) == 1)
  514. + device_reset(&pdev->dev);
  515. +
  516. + ret = devm_spi_register_master(&pdev->dev, master);
  517. + if (ret < 0) {
  518. + dev_err(&pdev->dev, "devm_spi_register_master error.\n");
  519. + goto err_master;
  520. + }
  521. +
  522. + return ret;
  523. +
  524. +err_master:
  525. + spi_master_put(master);
  526. + kfree(master);
  527. +err_clk:
  528. + clk_disable_unprepare(clk);
  529. +
  530. + return ret;
  531. +}
  532. +
  533. +static int rt2880_spi_remove(struct platform_device *pdev)
  534. +{
  535. + struct spi_master *master;
  536. + struct rt2880_spi *rs;
  537. +
  538. + master = dev_get_drvdata(&pdev->dev);
  539. + rs = spi_master_get_devdata(master);
  540. +
  541. + clk_disable_unprepare(rs->clk);
  542. + atomic_dec(&hw_reset_count);
  543. +
  544. + return 0;
  545. +}
  546. +
  547. +MODULE_ALIAS("platform:" DRIVER_NAME);
  548. +
  549. +static const struct of_device_id rt2880_spi_match[] = {
  550. + { .compatible = "ralink,rt2880-spi" },
  551. + {},
  552. +};
  553. +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
  554. +
  555. +static struct platform_driver rt2880_spi_driver = {
  556. + .driver = {
  557. + .name = DRIVER_NAME,
  558. + .owner = THIS_MODULE,
  559. + .of_match_table = rt2880_spi_match,
  560. + },
  561. + .probe = rt2880_spi_probe,
  562. + .remove = rt2880_spi_remove,
  563. +};
  564. +
  565. +module_platform_driver(rt2880_spi_driver);
  566. +
  567. +MODULE_DESCRIPTION("Ralink SPI driver");
  568. +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
  569. +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  570. +MODULE_LICENSE("GPL");