0045-i2c-add-mt7621-driver.patch 11 KB

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  1. From d5c54ff3d1db0a4348fa04d8e78f3bf6063e3afc Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Mon, 7 Dec 2015 17:21:27 +0100
  4. Subject: [PATCH 45/53] i2c: add mt7621 driver
  5. Signed-off-by: John Crispin <blogic@openwrt.org>
  6. ---
  7. drivers/i2c/busses/Kconfig | 4 +
  8. drivers/i2c/busses/Makefile | 1 +
  9. drivers/i2c/busses/i2c-mt7621.c | 303 +++++++++++++++++++++++++++++++++++++++
  10. 3 files changed, 308 insertions(+)
  11. create mode 100644 drivers/i2c/busses/i2c-mt7621.c
  12. --- a/drivers/i2c/busses/Kconfig
  13. +++ b/drivers/i2c/busses/Kconfig
  14. @@ -811,6 +811,11 @@ config I2C_RALINK
  15. depends on RALINK && !SOC_MT7621
  16. select OF_I2C
  17. +config I2C_MT7621
  18. + tristate "MT7621/MT7628 I2C Controller"
  19. + depends on RALINK && (SOC_MT7620 || SOC_MT7621)
  20. + select OF_I2C
  21. +
  22. config HAVE_S3C2410_I2C
  23. bool
  24. help
  25. --- a/drivers/i2c/busses/Makefile
  26. +++ b/drivers/i2c/busses/Makefile
  27. @@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
  28. obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
  29. obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
  30. obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
  31. +obj-$(CONFIG_I2C_MT7621) += i2c-mt7621.o
  32. obj-$(CONFIG_I2C_QUP) += i2c-qup.o
  33. obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
  34. obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
  35. --- /dev/null
  36. +++ b/drivers/i2c/busses/i2c-mt7621.c
  37. @@ -0,0 +1,433 @@
  38. +/*
  39. + * drivers/i2c/busses/i2c-mt7621.c
  40. + *
  41. + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
  42. + * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
  43. + *
  44. + * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
  45. + * (C) 2014 Sittisak <sittisaks@hotmail.com>
  46. + *
  47. + * This software is licensed under the terms of the GNU General Public
  48. + * License version 2, as published by the Free Software Foundation, and
  49. + * may be copied, distributed, and modified under those terms.
  50. + *
  51. + * This program is distributed in the hope that it will be useful,
  52. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  53. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  54. + * GNU General Public License for more details.
  55. + *
  56. + */
  57. +
  58. +#include <linux/interrupt.h>
  59. +#include <linux/kernel.h>
  60. +#include <linux/module.h>
  61. +#include <linux/reset.h>
  62. +#include <linux/delay.h>
  63. +#include <linux/slab.h>
  64. +#include <linux/init.h>
  65. +#include <linux/errno.h>
  66. +#include <linux/platform_device.h>
  67. +#include <linux/of_platform.h>
  68. +#include <linux/i2c.h>
  69. +#include <linux/io.h>
  70. +#include <linux/err.h>
  71. +#include <linux/clk.h>
  72. +
  73. +#define REG_SM0CFG0 0x08
  74. +#define REG_SM0DOUT 0x10
  75. +#define REG_SM0DIN 0x14
  76. +#define REG_SM0ST 0x18
  77. +#define REG_SM0AUTO 0x1C
  78. +#define REG_SM0CFG1 0x20
  79. +#define REG_SM0CFG2 0x28
  80. +#define REG_SM0CTL0 0x40
  81. +#define REG_SM0CTL1 0x44
  82. +#define REG_SM0D0 0x50
  83. +#define REG_SM0D1 0x54
  84. +#define REG_PINTEN 0x5C
  85. +#define REG_PINTST 0x60
  86. +#define REG_PINTCL 0x64
  87. +
  88. +/* REG_SM0CFG0 */
  89. +#define I2C_DEVADDR_MASK 0x7f
  90. +
  91. +/* REG_SM0ST */
  92. +#define I2C_DATARDY BIT(2)
  93. +#define I2C_SDOEMPTY BIT(1)
  94. +#define I2C_BUSY BIT(0)
  95. +
  96. +/* REG_SM0AUTO */
  97. +#define READ_CMD BIT(0)
  98. +
  99. +/* REG_SM0CFG1 */
  100. +#define BYTECNT_MAX 64
  101. +#define SET_BYTECNT(x) (x - 1)
  102. +
  103. +/* REG_SM0CFG2 */
  104. +#define AUTOMODE_EN BIT(0)
  105. +
  106. +/* REG_SM0CTL0 */
  107. +#define ODRAIN_HIGH_SM0 BIT(31)
  108. +#define VSYNC_SHIFT 28
  109. +#define VSYNC_MASK 0x3
  110. +#define VSYNC_PULSE (0x1 << VSYNC_SHIFT)
  111. +#define VSYNC_RISING (0x2 << VSYNC_SHIFT)
  112. +#define CLK_DIV_SHIFT 16
  113. +#define CLK_DIV_MASK 0xfff
  114. +#define DEG_CNT_SHIFT 8
  115. +#define DEG_CNT_MASK 0xff
  116. +#define WAIT_HIGH BIT(6)
  117. +#define DEG_EN BIT(5)
  118. +#define CS_STATUA BIT(4)
  119. +#define SCL_STATUS BIT(3)
  120. +#define SDA_STATUS BIT(2)
  121. +#define SM0_EN BIT(1)
  122. +#define SCL_STRECH BIT(0)
  123. +
  124. +/* REG_SM0CTL1 */
  125. +#define ACK_SHIFT 16
  126. +#define ACK_MASK 0xff
  127. +#define PGLEN_SHIFT 8
  128. +#define PGLEN_MASK 0x7
  129. +#define SM0_MODE_SHIFT 4
  130. +#define SM0_MODE_MASK 0x7
  131. +#define SM0_MODE_START 0x1
  132. +#define SM0_MODE_WRITE 0x2
  133. +#define SM0_MODE_STOP 0x3
  134. +#define SM0_MODE_READ_NACK 0x4
  135. +#define SM0_MODE_READ_ACK 0x5
  136. +#define SM0_TRI_BUSY BIT(0)
  137. +
  138. +/* timeout waiting for I2C devices to respond (clock streching) */
  139. +#define TIMEOUT_MS 1000
  140. +#define DELAY_INTERVAL_US 100
  141. +
  142. +struct mtk_i2c {
  143. + void __iomem *base;
  144. + struct clk *clk;
  145. + struct device *dev;
  146. + struct i2c_adapter adap;
  147. + u32 cur_clk;
  148. + u32 clk_div;
  149. + u32 flags;
  150. +};
  151. +
  152. +static void mtk_i2c_w32(struct mtk_i2c *i2c, u32 val, unsigned reg)
  153. +{
  154. + iowrite32(val, i2c->base + reg);
  155. +}
  156. +
  157. +static u32 mtk_i2c_r32(struct mtk_i2c *i2c, unsigned reg)
  158. +{
  159. + return ioread32(i2c->base + reg);
  160. +}
  161. +
  162. +static int poll_down_timeout(void __iomem *addr, u32 mask)
  163. +{
  164. + unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
  165. +
  166. + do {
  167. + if (!(readl_relaxed(addr) & mask))
  168. + return 0;
  169. +
  170. + usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
  171. + } while (time_before(jiffies, timeout));
  172. +
  173. + return (readl_relaxed(addr) & mask) ? -EAGAIN : 0;
  174. +}
  175. +
  176. +static int mtk_i2c_wait_idle(struct mtk_i2c *i2c)
  177. +{
  178. + int ret;
  179. +
  180. + ret = poll_down_timeout(i2c->base + REG_SM0ST, I2C_BUSY);
  181. + if (ret < 0)
  182. + dev_dbg(i2c->dev, "idle err(%d)\n", ret);
  183. +
  184. + return ret;
  185. +}
  186. +
  187. +static int poll_up_timeout(void __iomem *addr, u32 mask)
  188. +{
  189. + unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
  190. + u32 status;
  191. +
  192. + do {
  193. + status = readl_relaxed(addr);
  194. + if (status & mask)
  195. + return 0;
  196. + usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
  197. + } while (time_before(jiffies, timeout));
  198. +
  199. + return -ETIMEDOUT;
  200. +}
  201. +
  202. +static int mtk_i2c_wait_rx_done(struct mtk_i2c *i2c)
  203. +{
  204. + int ret;
  205. +
  206. + ret = poll_up_timeout(i2c->base + REG_SM0ST, I2C_DATARDY);
  207. + if (ret < 0)
  208. + dev_dbg(i2c->dev, "rx err(%d)\n", ret);
  209. +
  210. + return ret;
  211. +}
  212. +
  213. +static int mtk_i2c_wait_tx_done(struct mtk_i2c *i2c)
  214. +{
  215. + int ret;
  216. +
  217. + ret = poll_up_timeout(i2c->base + REG_SM0ST, I2C_SDOEMPTY);
  218. + if (ret < 0)
  219. + dev_dbg(i2c->dev, "tx err(%d)\n", ret);
  220. +
  221. + return ret;
  222. +}
  223. +
  224. +static void mtk_i2c_reset(struct mtk_i2c *i2c)
  225. +{
  226. + u32 reg;
  227. + device_reset(i2c->adap.dev.parent);
  228. + barrier();
  229. +
  230. + /* ctrl0 */
  231. + reg = ODRAIN_HIGH_SM0 | VSYNC_PULSE | (i2c->clk_div << CLK_DIV_SHIFT) |
  232. + WAIT_HIGH | SM0_EN;
  233. + mtk_i2c_w32(i2c, reg, REG_SM0CTL0);
  234. +
  235. + /* auto mode */
  236. + mtk_i2c_w32(i2c, AUTOMODE_EN, REG_SM0CFG2);
  237. +}
  238. +
  239. +static void mtk_i2c_dump_reg(struct mtk_i2c *i2c)
  240. +{
  241. + dev_dbg(i2c->dev, "cfg0 %08x, dout %08x, din %08x, " \
  242. + "status %08x, auto %08x, cfg1 %08x, " \
  243. + "cfg2 %08x, ctl0 %08x, ctl1 %08x\n",
  244. + mtk_i2c_r32(i2c, REG_SM0CFG0),
  245. + mtk_i2c_r32(i2c, REG_SM0DOUT),
  246. + mtk_i2c_r32(i2c, REG_SM0DIN),
  247. + mtk_i2c_r32(i2c, REG_SM0ST),
  248. + mtk_i2c_r32(i2c, REG_SM0AUTO),
  249. + mtk_i2c_r32(i2c, REG_SM0CFG1),
  250. + mtk_i2c_r32(i2c, REG_SM0CFG2),
  251. + mtk_i2c_r32(i2c, REG_SM0CTL0),
  252. + mtk_i2c_r32(i2c, REG_SM0CTL1));
  253. +}
  254. +
  255. +static int mtk_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
  256. + int num)
  257. +{
  258. + struct mtk_i2c *i2c;
  259. + struct i2c_msg *pmsg;
  260. + int i, j, ret;
  261. + u32 cmd;
  262. +
  263. + i2c = i2c_get_adapdata(adap);
  264. +
  265. + for (i = 0; i < num; i++) {
  266. + pmsg = &msgs[i];
  267. + cmd = 0;
  268. +
  269. + dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x\n",
  270. + pmsg->addr, pmsg->len, pmsg->flags);
  271. +
  272. + /* wait hardware idle */
  273. + if ((ret = mtk_i2c_wait_idle(i2c)))
  274. + goto err_timeout;
  275. +
  276. + if (pmsg->flags & I2C_M_TEN) {
  277. + dev_dbg(i2c->dev, "10 bits addr not supported\n");
  278. + return -EINVAL;
  279. + } else {
  280. + /* 7 bits address */
  281. + mtk_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,
  282. + REG_SM0CFG0);
  283. + }
  284. +
  285. + /* buffer length */
  286. + if (pmsg->len == 0) {
  287. + dev_dbg(i2c->dev, "length is 0\n");
  288. + return -EINVAL;
  289. + } else
  290. + mtk_i2c_w32(i2c, SET_BYTECNT(pmsg->len),
  291. + REG_SM0CFG1);
  292. +
  293. + j = 0;
  294. + if (pmsg->flags & I2C_M_RD) {
  295. + cmd |= READ_CMD;
  296. + /* start transfer */
  297. + barrier();
  298. + mtk_i2c_w32(i2c, cmd, REG_SM0AUTO);
  299. + do {
  300. + /* wait */
  301. + if ((ret = mtk_i2c_wait_rx_done(i2c)))
  302. + goto err_timeout;
  303. + /* read data */
  304. + if (pmsg->len)
  305. + pmsg->buf[j] = mtk_i2c_r32(i2c,
  306. + REG_SM0DIN);
  307. + j++;
  308. + } while (j < pmsg->len);
  309. + } else {
  310. + do {
  311. + /* write data */
  312. + if (pmsg->len)
  313. + mtk_i2c_w32(i2c, pmsg->buf[j],
  314. + REG_SM0DOUT);
  315. + /* start transfer */
  316. + if (j == 0) {
  317. + barrier();
  318. + mtk_i2c_w32(i2c, cmd, REG_SM0AUTO);
  319. + }
  320. + /* wait */
  321. + if ((ret = mtk_i2c_wait_tx_done(i2c)))
  322. + goto err_timeout;
  323. + j++;
  324. + } while (j < pmsg->len);
  325. + }
  326. + }
  327. + /* the return value is number of executed messages */
  328. + ret = i;
  329. +
  330. + return ret;
  331. +
  332. +err_timeout:
  333. + mtk_i2c_dump_reg(i2c);
  334. + mtk_i2c_reset(i2c);
  335. + return ret;
  336. +}
  337. +
  338. +static u32 mtk_i2c_func(struct i2c_adapter *a)
  339. +{
  340. + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  341. +}
  342. +
  343. +static const struct i2c_algorithm mtk_i2c_algo = {
  344. + .master_xfer = mtk_i2c_master_xfer,
  345. + .functionality = mtk_i2c_func,
  346. +};
  347. +
  348. +static const struct of_device_id i2c_mtk_dt_ids[] = {
  349. + { .compatible = "mediatek,mt7621-i2c" },
  350. + { /* sentinel */ }
  351. +};
  352. +
  353. +MODULE_DEVICE_TABLE(of, i2c_mtk_dt_ids);
  354. +
  355. +static struct i2c_adapter_quirks mtk_i2c_quirks = {
  356. + .max_write_len = BYTECNT_MAX,
  357. + .max_read_len = BYTECNT_MAX,
  358. +};
  359. +
  360. +static void mtk_i2c_init(struct mtk_i2c *i2c)
  361. +{
  362. + i2c->clk_div = clk_get_rate(i2c->clk) / i2c->cur_clk;
  363. + if (i2c->clk_div > CLK_DIV_MASK)
  364. + i2c->clk_div = CLK_DIV_MASK;
  365. +
  366. + mtk_i2c_reset(i2c);
  367. +}
  368. +
  369. +static int mtk_i2c_probe(struct platform_device *pdev)
  370. +{
  371. + struct resource *res;
  372. + struct mtk_i2c *i2c;
  373. + struct i2c_adapter *adap;
  374. + const struct of_device_id *match;
  375. + int ret;
  376. +
  377. + match = of_match_device(i2c_mtk_dt_ids, &pdev->dev);
  378. +
  379. + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  380. + if (!res) {
  381. + dev_err(&pdev->dev, "no memory resource found\n");
  382. + return -ENODEV;
  383. + }
  384. +
  385. + i2c = devm_kzalloc(&pdev->dev, sizeof(struct mtk_i2c), GFP_KERNEL);
  386. + if (!i2c) {
  387. + dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
  388. + return -ENOMEM;
  389. + }
  390. +
  391. + i2c->base = devm_ioremap_resource(&pdev->dev, res);
  392. + if (IS_ERR(i2c->base))
  393. + return PTR_ERR(i2c->base);
  394. +
  395. + i2c->clk = devm_clk_get(&pdev->dev, NULL);
  396. + if (IS_ERR(i2c->clk)) {
  397. + dev_err(&pdev->dev, "no clock defined\n");
  398. + return -ENODEV;
  399. + }
  400. + clk_prepare_enable(i2c->clk);
  401. + i2c->dev = &pdev->dev;
  402. +
  403. + if (of_property_read_u32(pdev->dev.of_node,
  404. + "clock-frequency", &i2c->cur_clk))
  405. + i2c->cur_clk = 100000;
  406. +
  407. + adap = &i2c->adap;
  408. + adap->owner = THIS_MODULE;
  409. + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
  410. + adap->algo = &mtk_i2c_algo;
  411. + adap->retries = 3;
  412. + adap->dev.parent = &pdev->dev;
  413. + i2c_set_adapdata(adap, i2c);
  414. + adap->dev.of_node = pdev->dev.of_node;
  415. + strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
  416. + adap->quirks = &mtk_i2c_quirks;
  417. +
  418. + platform_set_drvdata(pdev, i2c);
  419. +
  420. + mtk_i2c_init(i2c);
  421. +
  422. + ret = i2c_add_adapter(adap);
  423. + if (ret < 0) {
  424. + dev_err(&pdev->dev, "failed to add adapter\n");
  425. + clk_disable_unprepare(i2c->clk);
  426. + return ret;
  427. + }
  428. +
  429. + dev_info(&pdev->dev, "clock %uKHz, re-start not support\n",
  430. + i2c->cur_clk/1000);
  431. +
  432. + return ret;
  433. +}
  434. +
  435. +static int mtk_i2c_remove(struct platform_device *pdev)
  436. +{
  437. + struct mtk_i2c *i2c = platform_get_drvdata(pdev);
  438. +
  439. + i2c_del_adapter(&i2c->adap);
  440. + clk_disable_unprepare(i2c->clk);
  441. +
  442. + return 0;
  443. +}
  444. +
  445. +static struct platform_driver mtk_i2c_driver = {
  446. + .probe = mtk_i2c_probe,
  447. + .remove = mtk_i2c_remove,
  448. + .driver = {
  449. + .owner = THIS_MODULE,
  450. + .name = "i2c-mt7621",
  451. + .of_match_table = i2c_mtk_dt_ids,
  452. + },
  453. +};
  454. +
  455. +static int __init i2c_mtk_init (void)
  456. +{
  457. + return platform_driver_register(&mtk_i2c_driver);
  458. +}
  459. +subsys_initcall(i2c_mtk_init);
  460. +
  461. +static void __exit i2c_mtk_exit (void)
  462. +{
  463. + platform_driver_unregister(&mtk_i2c_driver);
  464. +}
  465. +module_exit(i2c_mtk_exit);
  466. +
  467. +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
  468. +MODULE_DESCRIPTION("MT7621 I2c host driver");
  469. +MODULE_LICENSE("GPL");
  470. +MODULE_ALIAS("platform:MT7621-I2C");