1
0

0080-MIPS-ralink-fix-USB-frequency-scaling.patch 1.1 KB

12345678910111213141516171819202122232425262728
  1. From ae28413b3b8901ea00af3571e1c90d0228976e16 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Mon, 4 Jan 2016 20:23:57 +0100
  4. Subject: [PATCH 80/81] MIPS: ralink: fix USB frequency scaling
  5. Commit 418d29c87061 ("MIPS: ralink: Unify SoC id handling") was not fully
  6. correct. The logic for the SoC check got inverted. We need to check if it
  7. is not a MT76x8.
  8. Signed-off-by: John Crispin <blogic@openwrt.org>
  9. Cc: linux-mips@linux-mips.org
  10. Patchwork: https://patchwork.linux-mips.org/patch/11992/
  11. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  12. ---
  13. arch/mips/ralink/mt7620.c | 2 +-
  14. 1 file changed, 1 insertion(+), 1 deletion(-)
  15. --- a/arch/mips/ralink/mt7620.c
  16. +++ b/arch/mips/ralink/mt7620.c
  17. @@ -462,7 +462,7 @@ void __init ralink_clk_init(void)
  18. ralink_clk_add("10000e00.uart2", periph_rate);
  19. ralink_clk_add("10180000.wmac", xtal_rate);
  20. - if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
  21. + if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
  22. /*
  23. * When the CPU goes into sleep mode, the BUS clock will be
  24. * too low for USB to function properly. Adjust the busses