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0503-net-next-mediatek-add-switch-driver-for-mt7620.patch 11 KB

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  1. From 322a9598692943961791ac6e5a3f385b379dcdc3 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Mon, 14 Dec 2015 21:23:18 +0100
  4. Subject: [PATCH 503/513] net-next: mediatek: add switch driver for mt7620
  5. This driver is very basic and only provides basic init and irq support.
  6. Switchdev support for this device will follow.
  7. Signed-off-by: John Crispin <blogic@openwrt.org>
  8. ---
  9. drivers/net/ethernet/mediatek/gsw_mt7620.c | 255 ++++++++++++++++++++++++++++
  10. drivers/net/ethernet/mediatek/gsw_mt7620.h | 117 +++++++++++++
  11. 2 files changed, 372 insertions(+)
  12. create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7620.c
  13. create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7620.h
  14. --- /dev/null
  15. +++ b/drivers/net/ethernet/mediatek/gsw_mt7620.c
  16. @@ -0,0 +1,255 @@
  17. +/* This program is free software; you can redistribute it and/or modify
  18. + * it under the terms of the GNU General Public License as published by
  19. + * the Free Software Foundation; version 2 of the License
  20. + *
  21. + * This program is distributed in the hope that it will be useful,
  22. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. + * GNU General Public License for more details.
  25. + *
  26. + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  27. + * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  28. + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  29. + */
  30. +
  31. +#include <linux/module.h>
  32. +#include <linux/kernel.h>
  33. +#include <linux/types.h>
  34. +#include <linux/platform_device.h>
  35. +#include <linux/of_device.h>
  36. +#include <linux/of_irq.h>
  37. +
  38. +#include <ralink_regs.h>
  39. +
  40. +#include "mtk_eth_soc.h"
  41. +#include "gsw_mt7620.h"
  42. +
  43. +void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
  44. +{
  45. + iowrite32(val, gsw->base + reg);
  46. +}
  47. +
  48. +u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
  49. +{
  50. + return ioread32(gsw->base + reg);
  51. +}
  52. +
  53. +static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
  54. +{
  55. + struct fe_priv *priv = (struct fe_priv *)_priv;
  56. + struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
  57. + u32 status;
  58. + int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
  59. +
  60. + status = mtk_switch_r32(gsw, GSW_REG_ISR);
  61. + if (status & PORT_IRQ_ST_CHG)
  62. + for (i = 0; i <= max; i++) {
  63. + u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i));
  64. + int link = status & 0x1;
  65. +
  66. + if (link != priv->link[i])
  67. + mt7620_print_link_state(priv, i, link,
  68. + (status >> 2) & 3,
  69. + (status & 0x2));
  70. +
  71. + priv->link[i] = link;
  72. + }
  73. + mtk_switch_w32(gsw, status, GSW_REG_ISR);
  74. +
  75. + return IRQ_HANDLED;
  76. +}
  77. +
  78. +static void mt7620_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
  79. +{
  80. + u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
  81. +
  82. + rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
  83. + mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
  84. +
  85. + if (of_property_read_bool(np, "mediatek,mt7530")) {
  86. + u32 val;
  87. +
  88. + /* turn off ephy and set phy base addr to 12 */
  89. + mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
  90. + (0x1f << 24) | (0xc << 16),
  91. + GSW_REG_GPC1);
  92. +
  93. + /* set MT7530 central align */
  94. + val = mt7530_mdio_r32(gsw, 0x7830);
  95. + val &= ~BIT(0);
  96. + val |= BIT(1);
  97. + mt7530_mdio_w32(gsw, 0x7830, val);
  98. +
  99. + val = mt7530_mdio_r32(gsw, 0x7a40);
  100. + val &= ~BIT(30);
  101. + mt7530_mdio_w32(gsw, 0x7a40, val);
  102. +
  103. + mt7530_mdio_w32(gsw, 0x7a78, 0x855);
  104. + } else {
  105. + /* global page 4 */
  106. + _mt7620_mii_write(gsw, 1, 31, 0x4000);
  107. +
  108. + _mt7620_mii_write(gsw, 1, 17, 0x7444);
  109. + if (is_BGA)
  110. + _mt7620_mii_write(gsw, 1, 19, 0x0114);
  111. + else
  112. + _mt7620_mii_write(gsw, 1, 19, 0x0117);
  113. +
  114. + _mt7620_mii_write(gsw, 1, 22, 0x10cf);
  115. + _mt7620_mii_write(gsw, 1, 25, 0x6212);
  116. + _mt7620_mii_write(gsw, 1, 26, 0x0777);
  117. + _mt7620_mii_write(gsw, 1, 29, 0x4000);
  118. + _mt7620_mii_write(gsw, 1, 28, 0xc077);
  119. + _mt7620_mii_write(gsw, 1, 24, 0x0000);
  120. +
  121. + /* global page 3 */
  122. + _mt7620_mii_write(gsw, 1, 31, 0x3000);
  123. + _mt7620_mii_write(gsw, 1, 17, 0x4838);
  124. +
  125. + /* global page 2 */
  126. + _mt7620_mii_write(gsw, 1, 31, 0x2000);
  127. + if (is_BGA) {
  128. + _mt7620_mii_write(gsw, 1, 21, 0x0515);
  129. + _mt7620_mii_write(gsw, 1, 22, 0x0053);
  130. + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
  131. + _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
  132. + _mt7620_mii_write(gsw, 1, 25, 0x0fad);
  133. + _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
  134. + } else {
  135. + _mt7620_mii_write(gsw, 1, 21, 0x0517);
  136. + _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
  137. + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
  138. + _mt7620_mii_write(gsw, 1, 24, 0x0aab);
  139. + _mt7620_mii_write(gsw, 1, 25, 0x00ae);
  140. + _mt7620_mii_write(gsw, 1, 26, 0x0fff);
  141. + }
  142. + /* global page 1 */
  143. + _mt7620_mii_write(gsw, 1, 31, 0x1000);
  144. + _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
  145. + }
  146. +
  147. + /* global page 0 */
  148. + _mt7620_mii_write(gsw, 1, 31, 0x8000);
  149. + _mt7620_mii_write(gsw, 0, 30, 0xa000);
  150. + _mt7620_mii_write(gsw, 1, 30, 0xa000);
  151. + _mt7620_mii_write(gsw, 2, 30, 0xa000);
  152. + _mt7620_mii_write(gsw, 3, 30, 0xa000);
  153. +
  154. + _mt7620_mii_write(gsw, 0, 4, 0x05e1);
  155. + _mt7620_mii_write(gsw, 1, 4, 0x05e1);
  156. + _mt7620_mii_write(gsw, 2, 4, 0x05e1);
  157. + _mt7620_mii_write(gsw, 3, 4, 0x05e1);
  158. +
  159. + /* global page 2 */
  160. + _mt7620_mii_write(gsw, 1, 31, 0xa000);
  161. + _mt7620_mii_write(gsw, 0, 16, 0x1111);
  162. + _mt7620_mii_write(gsw, 1, 16, 0x1010);
  163. + _mt7620_mii_write(gsw, 2, 16, 0x1515);
  164. + _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
  165. +
  166. + /* CPU Port6 Force Link 1G, FC ON */
  167. + mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
  168. +
  169. + /* Set Port 6 as CPU Port */
  170. + mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
  171. +
  172. + /* setup port 4 */
  173. + if (gsw->port4 == PORT4_EPHY) {
  174. + u32 val = rt_sysc_r32(SYSC_REG_CFG1);
  175. +
  176. + val |= 3 << 14;
  177. + rt_sysc_w32(val, SYSC_REG_CFG1);
  178. + _mt7620_mii_write(gsw, 4, 30, 0xa000);
  179. + _mt7620_mii_write(gsw, 4, 4, 0x05e1);
  180. + _mt7620_mii_write(gsw, 4, 16, 0x1313);
  181. + pr_info("gsw: setting port4 to ephy mode\n");
  182. + }
  183. +}
  184. +
  185. +static const struct of_device_id mediatek_gsw_match[] = {
  186. + { .compatible = "mediatek,mt7620-gsw" },
  187. + {},
  188. +};
  189. +MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
  190. +
  191. +int mtk_gsw_init(struct fe_priv *priv)
  192. +{
  193. + struct device_node *np = priv->switch_np;
  194. + struct platform_device *pdev = of_find_device_by_node(np);
  195. + struct mt7620_gsw *gsw;
  196. +
  197. + if (!pdev)
  198. + return -ENODEV;
  199. +
  200. + if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
  201. + return -EINVAL;
  202. +
  203. + gsw = platform_get_drvdata(pdev);
  204. + priv->soc->swpriv = gsw;
  205. +
  206. + mt7620_hw_init(gsw, np);
  207. +
  208. + if (gsw->irq) {
  209. + request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
  210. + "gsw", priv);
  211. + mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
  212. + }
  213. +
  214. + return 0;
  215. +}
  216. +
  217. +static int mt7620_gsw_probe(struct platform_device *pdev)
  218. +{
  219. + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  220. + const char *port4 = NULL;
  221. + struct mt7620_gsw *gsw;
  222. + struct device_node *np = pdev->dev.of_node;
  223. +
  224. + gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
  225. + if (!gsw)
  226. + return -ENOMEM;
  227. +
  228. + gsw->base = devm_ioremap_resource(&pdev->dev, res);
  229. + if (!gsw->base)
  230. + return -EADDRNOTAVAIL;
  231. +
  232. + gsw->dev = &pdev->dev;
  233. +
  234. + of_property_read_string(np, "mediatek,port4", &port4);
  235. + if (port4 && !strcmp(port4, "ephy"))
  236. + gsw->port4 = PORT4_EPHY;
  237. + else if (port4 && !strcmp(port4, "gmac"))
  238. + gsw->port4 = PORT4_EXT;
  239. + else
  240. + gsw->port4 = PORT4_EPHY;
  241. +
  242. + gsw->irq = platform_get_irq(pdev, 0);
  243. +
  244. + platform_set_drvdata(pdev, gsw);
  245. +
  246. + return 0;
  247. +}
  248. +
  249. +static int mt7620_gsw_remove(struct platform_device *pdev)
  250. +{
  251. + platform_set_drvdata(pdev, NULL);
  252. +
  253. + return 0;
  254. +}
  255. +
  256. +static struct platform_driver gsw_driver = {
  257. + .probe = mt7620_gsw_probe,
  258. + .remove = mt7620_gsw_remove,
  259. + .driver = {
  260. + .name = "mt7620-gsw",
  261. + .owner = THIS_MODULE,
  262. + .of_match_table = mediatek_gsw_match,
  263. + },
  264. +};
  265. +
  266. +module_platform_driver(gsw_driver);
  267. +
  268. +MODULE_LICENSE("GPL");
  269. +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
  270. +MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
  271. +MODULE_VERSION(MTK_FE_DRV_VERSION);
  272. --- /dev/null
  273. +++ b/drivers/net/ethernet/mediatek/gsw_mt7620.h
  274. @@ -0,0 +1,117 @@
  275. +/* This program is free software; you can redistribute it and/or modify
  276. + * it under the terms of the GNU General Public License as published by
  277. + * the Free Software Foundation; version 2 of the License
  278. + *
  279. + * This program is distributed in the hope that it will be useful,
  280. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  281. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  282. + * GNU General Public License for more details.
  283. + *
  284. + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  285. + * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  286. + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  287. + */
  288. +
  289. +#ifndef _RALINK_GSW_MT7620_H__
  290. +#define _RALINK_GSW_MT7620_H__
  291. +
  292. +#define GSW_REG_PHY_TIMEOUT (5 * HZ)
  293. +
  294. +#ifdef CONFIG_SOC_MT7621
  295. +#define MT7620A_GSW_REG_PIAC 0x0004
  296. +#else
  297. +#define MT7620A_GSW_REG_PIAC 0x7004
  298. +#endif
  299. +
  300. +#define GSW_NUM_VLANS 16
  301. +#define GSW_NUM_VIDS 4096
  302. +#define GSW_NUM_PORTS 7
  303. +#define GSW_PORT6 6
  304. +
  305. +#define GSW_MDIO_ACCESS BIT(31)
  306. +#define GSW_MDIO_READ BIT(19)
  307. +#define GSW_MDIO_WRITE BIT(18)
  308. +#define GSW_MDIO_START BIT(16)
  309. +#define GSW_MDIO_ADDR_SHIFT 20
  310. +#define GSW_MDIO_REG_SHIFT 25
  311. +
  312. +#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
  313. +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
  314. +#define GSW_REG_SMACCR0 0x3fE4
  315. +#define GSW_REG_SMACCR1 0x3fE8
  316. +#define GSW_REG_CKGCR 0x3ff0
  317. +
  318. +#define GSW_REG_IMR 0x7008
  319. +#define GSW_REG_ISR 0x700c
  320. +#define GSW_REG_GPC1 0x7014
  321. +
  322. +#define SYSC_REG_CHIP_REV_ID 0x0c
  323. +#define SYSC_REG_CFG1 0x14
  324. +#define RST_CTRL_MCM BIT(2)
  325. +#define SYSC_PAD_RGMII2_MDIO 0x58
  326. +#define SYSC_GPIO_MODE 0x60
  327. +
  328. +#define PORT_IRQ_ST_CHG 0x7f
  329. +
  330. +#ifdef CONFIG_SOC_MT7621
  331. +#define ESW_PHY_POLLING 0x0000
  332. +#else
  333. +#define ESW_PHY_POLLING 0x7000
  334. +#endif
  335. +
  336. +#define PMCR_IPG BIT(18)
  337. +#define PMCR_MAC_MODE BIT(16)
  338. +#define PMCR_FORCE BIT(15)
  339. +#define PMCR_TX_EN BIT(14)
  340. +#define PMCR_RX_EN BIT(13)
  341. +#define PMCR_BACKOFF BIT(9)
  342. +#define PMCR_BACKPRES BIT(8)
  343. +#define PMCR_RX_FC BIT(5)
  344. +#define PMCR_TX_FC BIT(4)
  345. +#define PMCR_SPEED(_x) (_x << 2)
  346. +#define PMCR_DUPLEX BIT(1)
  347. +#define PMCR_LINK BIT(0)
  348. +
  349. +#define PHY_AN_EN BIT(31)
  350. +#define PHY_PRE_EN BIT(30)
  351. +#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
  352. +
  353. +enum {
  354. + /* Global attributes. */
  355. + GSW_ATTR_ENABLE_VLAN,
  356. + /* Port attributes. */
  357. + GSW_ATTR_PORT_UNTAG,
  358. +};
  359. +
  360. +enum {
  361. + PORT4_EPHY = 0,
  362. + PORT4_EXT,
  363. +};
  364. +
  365. +struct mt7620_gsw {
  366. + struct device *dev;
  367. + void __iomem *base;
  368. + int irq;
  369. + int port4;
  370. + unsigned long int autopoll;
  371. +};
  372. +
  373. +void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
  374. +u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
  375. +int mtk_gsw_init(struct fe_priv *priv);
  376. +
  377. +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
  378. +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
  379. +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
  380. +int mt7620_has_carrier(struct fe_priv *priv);
  381. +void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
  382. + int speed, int duplex);
  383. +
  384. +void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
  385. +u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
  386. +
  387. +u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
  388. + u32 phy_register, u32 write_data);
  389. +u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);
  390. +
  391. +#endif