0505-net-next-mediatek-add-support-for-rt2880.patch 9.6 KB

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  1. From f8c8f4bd2a13e0cc060c93812377373d436f7f02 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Wed, 18 Nov 2015 03:13:05 +0100
  4. Subject: [PATCH 505/513] net-next: mediatek: add support for rt2880
  5. rt2880 is the oldest SoC with this core. It has a single gBit port that will
  6. normally be attached to an external phy of switch. The patch also adds the
  7. code required to drive the mdio bus.
  8. Signed-off-by: John Crispin <blogic@openwrt.org>
  9. Signed-off-by: Felix Fietkau <nbd@nbd.name>
  10. Signed-off-by: Michael Lee <igvtee@gmail.com>
  11. ---
  12. drivers/net/ethernet/mediatek/mdio_rt2880.c | 222 +++++++++++++++++++++++++++
  13. drivers/net/ethernet/mediatek/mdio_rt2880.h | 23 +++
  14. drivers/net/ethernet/mediatek/soc_rt2880.c | 76 +++++++++
  15. 3 files changed, 321 insertions(+)
  16. create mode 100644 drivers/net/ethernet/mediatek/mdio_rt2880.c
  17. create mode 100644 drivers/net/ethernet/mediatek/mdio_rt2880.h
  18. create mode 100644 drivers/net/ethernet/mediatek/soc_rt2880.c
  19. --- /dev/null
  20. +++ b/drivers/net/ethernet/mediatek/mdio_rt2880.c
  21. @@ -0,0 +1,222 @@
  22. +/* This program is free software; you can redistribute it and/or modify
  23. + * it under the terms of the GNU General Public License as published by
  24. + * the Free Software Foundation; version 2 of the License
  25. + *
  26. + * This program is distributed in the hope that it will be useful,
  27. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  28. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  29. + * GNU General Public License for more details.
  30. + *
  31. + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  32. + * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  33. + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  34. + */
  35. +
  36. +#include <linux/module.h>
  37. +#include <linux/kernel.h>
  38. +#include <linux/types.h>
  39. +#include <linux/of_net.h>
  40. +#include <linux/of_mdio.h>
  41. +
  42. +#include "mtk_eth_soc.h"
  43. +#include "mdio_rt2880.h"
  44. +#include "mdio.h"
  45. +
  46. +#define FE_MDIO_RETRY 1000
  47. +
  48. +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
  49. +{
  50. + switch (priv->phy->speed[0]) {
  51. + case SPEED_1000:
  52. + return "1000";
  53. + case SPEED_100:
  54. + return "100";
  55. + case SPEED_10:
  56. + return "10";
  57. + }
  58. +
  59. + return "?";
  60. +}
  61. +
  62. +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
  63. +{
  64. + u32 mdio_cfg;
  65. +
  66. + if (!priv->link[0]) {
  67. + netif_carrier_off(priv->netdev);
  68. + netdev_info(priv->netdev, "link down\n");
  69. + return;
  70. + }
  71. +
  72. + mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
  73. + FE_MDIO_CFG_RX_CLK_SKEW_200 |
  74. + FE_MDIO_CFG_GP1_FRC_EN;
  75. +
  76. + if (priv->phy->duplex[0] == DUPLEX_FULL)
  77. + mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
  78. +
  79. + if (priv->phy->tx_fc[0])
  80. + mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
  81. +
  82. + if (priv->phy->rx_fc[0])
  83. + mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
  84. +
  85. + switch (priv->phy->speed[0]) {
  86. + case SPEED_10:
  87. + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
  88. + break;
  89. + case SPEED_100:
  90. + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
  91. + break;
  92. + case SPEED_1000:
  93. + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
  94. + break;
  95. + default:
  96. + BUG();
  97. + }
  98. +
  99. + fe_w32(mdio_cfg, FE_MDIO_CFG);
  100. +
  101. + netif_carrier_on(priv->netdev);
  102. + netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
  103. + rt2880_speed_str(priv),
  104. + (priv->phy->duplex[0] == DUPLEX_FULL) ? "Full" : "Half");
  105. +}
  106. +
  107. +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
  108. +{
  109. + int retries;
  110. +
  111. + retries = FE_MDIO_RETRY;
  112. + while (1) {
  113. + u32 t;
  114. +
  115. + t = fe_r32(FE_MDIO_ACCESS);
  116. + if ((t & BIT(31)) == 0)
  117. + return 0;
  118. +
  119. + if (retries-- == 0)
  120. + break;
  121. +
  122. + udelay(1);
  123. + }
  124. +
  125. + dev_err(priv->device, "MDIO operation timed out\n");
  126. + return -ETIMEDOUT;
  127. +}
  128. +
  129. +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
  130. +{
  131. + struct fe_priv *priv = bus->priv;
  132. + int err;
  133. + u32 t;
  134. +
  135. + err = rt2880_mdio_wait_ready(priv);
  136. + if (err)
  137. + return 0xffff;
  138. +
  139. + t = (phy_addr << 24) | (phy_reg << 16);
  140. + fe_w32(t, FE_MDIO_ACCESS);
  141. + t |= BIT(31);
  142. + fe_w32(t, FE_MDIO_ACCESS);
  143. +
  144. + err = rt2880_mdio_wait_ready(priv);
  145. + if (err)
  146. + return 0xffff;
  147. +
  148. + pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
  149. + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
  150. +
  151. + return fe_r32(FE_MDIO_ACCESS) & 0xffff;
  152. +}
  153. +
  154. +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
  155. +{
  156. + struct fe_priv *priv = bus->priv;
  157. + int err;
  158. + u32 t;
  159. +
  160. + pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
  161. + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
  162. +
  163. + err = rt2880_mdio_wait_ready(priv);
  164. + if (err)
  165. + return err;
  166. +
  167. + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
  168. + fe_w32(t, FE_MDIO_ACCESS);
  169. + t |= BIT(31);
  170. + fe_w32(t, FE_MDIO_ACCESS);
  171. +
  172. + return rt2880_mdio_wait_ready(priv);
  173. +}
  174. +
  175. +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
  176. +{
  177. + const __be32 *id = of_get_property(np, "reg", NULL);
  178. + const __be32 *link;
  179. + int size;
  180. + int phy_mode;
  181. +
  182. + if (!id || (be32_to_cpu(*id) != 0)) {
  183. + pr_err("%s: invalid port id\n", np->name);
  184. + return;
  185. + }
  186. +
  187. + priv->phy->phy_fixed[0] = of_get_property(np,
  188. + "mediatek,fixed-link", &size);
  189. + if (priv->phy->phy_fixed[0] &&
  190. + (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
  191. + pr_err("%s: invalid fixed link property\n", np->name);
  192. + priv->phy->phy_fixed[0] = NULL;
  193. + return;
  194. + }
  195. +
  196. + phy_mode = of_get_phy_mode(np);
  197. + switch (phy_mode) {
  198. + case PHY_INTERFACE_MODE_RGMII:
  199. + break;
  200. + case PHY_INTERFACE_MODE_MII:
  201. + break;
  202. + case PHY_INTERFACE_MODE_RMII:
  203. + break;
  204. + default:
  205. + if (!priv->phy->phy_fixed[0])
  206. + dev_err(priv->device, "port %d - invalid phy mode\n",
  207. + priv->phy->speed[0]);
  208. + break;
  209. + }
  210. +
  211. + priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
  212. + if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
  213. + return;
  214. +
  215. + if (priv->phy->phy_fixed[0]) {
  216. + link = priv->phy->phy_fixed[0];
  217. + priv->phy->speed[0] = be32_to_cpup(link++);
  218. + priv->phy->duplex[0] = be32_to_cpup(link++);
  219. + priv->phy->tx_fc[0] = be32_to_cpup(link++);
  220. + priv->phy->rx_fc[0] = be32_to_cpup(link++);
  221. +
  222. + priv->link[0] = 1;
  223. + switch (priv->phy->speed[0]) {
  224. + case SPEED_10:
  225. + break;
  226. + case SPEED_100:
  227. + break;
  228. + case SPEED_1000:
  229. + break;
  230. + default:
  231. + dev_err(priv->device, "invalid link speed: %d\n",
  232. + priv->phy->speed[0]);
  233. + priv->phy->phy_fixed[0] = 0;
  234. + return;
  235. + }
  236. + dev_info(priv->device, "using fixed link parameters\n");
  237. + rt2880_mdio_link_adjust(priv, 0);
  238. + return;
  239. + }
  240. +
  241. + if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0])
  242. + fe_connect_phy_node(priv, priv->phy->phy_node[0]);
  243. +}
  244. --- /dev/null
  245. +++ b/drivers/net/ethernet/mediatek/mdio_rt2880.h
  246. @@ -0,0 +1,23 @@
  247. +/* This program is free software; you can redistribute it and/or modify
  248. + * it under the terms of the GNU General Public License as published by
  249. + * the Free Software Foundation; version 2 of the License
  250. + *
  251. + * This program is distributed in the hope that it will be useful,
  252. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  253. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  254. + * GNU General Public License for more details.
  255. + *
  256. + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  257. + * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  258. + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  259. + */
  260. +
  261. +#ifndef _RALINK_MDIO_RT2880_H__
  262. +#define _RALINK_MDIO_RT2880_H__
  263. +
  264. +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
  265. +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
  266. +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
  267. +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
  268. +
  269. +#endif
  270. --- /dev/null
  271. +++ b/drivers/net/ethernet/mediatek/soc_rt2880.c
  272. @@ -0,0 +1,76 @@
  273. +/* This program is free software; you can redistribute it and/or modify
  274. + * it under the terms of the GNU General Public License as published by
  275. + * the Free Software Foundation; version 2 of the License
  276. + *
  277. + * This program is distributed in the hope that it will be useful,
  278. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  279. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  280. + * GNU General Public License for more details.
  281. + *
  282. + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  283. + * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  284. + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  285. + */
  286. +
  287. +#include <linux/module.h>
  288. +
  289. +#include <asm/mach-ralink/ralink_regs.h>
  290. +
  291. +#include "mtk_eth_soc.h"
  292. +#include "mdio_rt2880.h"
  293. +
  294. +#define RT2880_RESET_FE BIT(18)
  295. +
  296. +static void rt2880_init_data(struct fe_soc_data *data,
  297. + struct net_device *netdev)
  298. +{
  299. + struct fe_priv *priv = netdev_priv(netdev);
  300. +
  301. + priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
  302. + FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
  303. + netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX;
  304. + /* this should work according to the datasheet but actually does not*/
  305. + /* netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM; */
  306. +}
  307. +
  308. +void rt2880_fe_reset(void)
  309. +{
  310. + fe_reset(RT2880_RESET_FE);
  311. +}
  312. +
  313. +static int rt2880_fwd_config(struct fe_priv *priv)
  314. +{
  315. + int ret;
  316. +
  317. + ret = fe_set_clock_cycle(priv);
  318. + if (ret)
  319. + return ret;
  320. +
  321. + fe_fwd_config(priv);
  322. + fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
  323. + fe_csum_config(priv);
  324. +
  325. + return ret;
  326. +}
  327. +
  328. +struct fe_soc_data rt2880_data = {
  329. + .init_data = rt2880_init_data,
  330. + .reset_fe = rt2880_fe_reset,
  331. + .fwd_config = rt2880_fwd_config,
  332. + .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
  333. + .checksum_bit = RX_DMA_L4VALID,
  334. + .rx_int = FE_RX_DONE_INT,
  335. + .tx_int = FE_TX_DONE_INT,
  336. + .status_int = FE_CNT_GDM_AF,
  337. + .mdio_read = rt2880_mdio_read,
  338. + .mdio_write = rt2880_mdio_write,
  339. + .mdio_adjust_link = rt2880_mdio_link_adjust,
  340. + .port_init = rt2880_port_init,
  341. +};
  342. +
  343. +const struct of_device_id of_fe_match[] = {
  344. + { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
  345. + {},
  346. +};
  347. +
  348. +MODULE_DEVICE_TABLE(of, of_fe_match);