022-bcma-from-4.8.patch 1.8 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152
  1. --- a/drivers/bcma/Kconfig
  2. +++ b/drivers/bcma/Kconfig
  3. @@ -76,9 +76,16 @@ config BCMA_PFLASH
  4. default y
  5. config BCMA_SFLASH
  6. - bool
  7. - depends on BCMA_DRIVER_MIPS
  8. + bool "ChipCommon-attached serial flash support"
  9. + depends on BCMA_HOST_SOC
  10. default y
  11. + help
  12. + Some cheap devices have serial flash connected to the ChipCommon
  13. + instead of independent SPI controller. It requires using a separated
  14. + driver that implements ChipCommon specific interface communication.
  15. +
  16. + Enabling this symbol will let bcma recognize serial flash and register
  17. + it as platform device.
  18. config BCMA_NFLASH
  19. bool
  20. --- a/drivers/bcma/driver_chipcommon_b.c
  21. +++ b/drivers/bcma/driver_chipcommon_b.c
  22. @@ -33,11 +33,12 @@ static bool bcma_wait_reg(struct bcma_bu
  23. void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
  24. {
  25. struct bcma_bus *bus = ccb->core->bus;
  26. + void __iomem *mii = ccb->mii;
  27. - writel(offset, ccb->mii + 0x00);
  28. - bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
  29. - writel(value, ccb->mii + 0x04);
  30. - bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
  31. + writel(offset, mii + BCMA_CCB_MII_MNG_CTL);
  32. + bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100);
  33. + writel(value, mii + BCMA_CCB_MII_MNG_CMD_DATA);
  34. + bcma_wait_reg(bus, mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, 100);
  35. }
  36. EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
  37. --- a/include/linux/bcma/bcma_driver_chipcommon.h
  38. +++ b/include/linux/bcma/bcma_driver_chipcommon.h
  39. @@ -504,6 +504,9 @@
  40. #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
  41. #define BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
  42. +#define BCMA_CCB_MII_MNG_CTL 0x0000
  43. +#define BCMA_CCB_MII_MNG_CMD_DATA 0x0004
  44. +
  45. /* BCM4331 ChipControl numbers. */
  46. #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
  47. #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */