ar8216.c 53 KB

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  1. /*
  2. * ar8216.c: AR8216 switch driver
  3. *
  4. * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
  5. * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version 2
  10. * of the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/if.h>
  18. #include <linux/module.h>
  19. #include <linux/init.h>
  20. #include <linux/list.h>
  21. #include <linux/if_ether.h>
  22. #include <linux/skbuff.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/netlink.h>
  25. #include <linux/bitops.h>
  26. #include <net/genetlink.h>
  27. #include <linux/switch.h>
  28. #include <linux/delay.h>
  29. #include <linux/phy.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/etherdevice.h>
  32. #include <linux/lockdep.h>
  33. #include <linux/ar8216_platform.h>
  34. #include <linux/workqueue.h>
  35. #include <linux/version.h>
  36. #include "ar8216.h"
  37. extern const struct ar8xxx_chip ar8327_chip;
  38. extern const struct ar8xxx_chip ar8337_chip;
  39. #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
  40. #define MIB_DESC(_s , _o, _n) \
  41. { \
  42. .size = (_s), \
  43. .offset = (_o), \
  44. .name = (_n), \
  45. }
  46. static const struct ar8xxx_mib_desc ar8216_mibs[] = {
  47. MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
  48. MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
  49. MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
  50. MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
  51. MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
  52. MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
  53. MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
  54. MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
  55. MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
  56. MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
  57. MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
  58. MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
  59. MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
  60. MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
  61. MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
  62. MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
  63. MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
  64. MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
  65. MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
  66. MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
  67. MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
  68. MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
  69. MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
  70. MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
  71. MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
  72. MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
  73. MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
  74. MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
  75. MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
  76. MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
  77. MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
  78. MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
  79. MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
  80. MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
  81. MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
  82. MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
  83. MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
  84. };
  85. const struct ar8xxx_mib_desc ar8236_mibs[39] = {
  86. MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
  87. MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
  88. MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
  89. MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
  90. MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
  91. MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
  92. MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
  93. MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
  94. MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
  95. MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
  96. MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
  97. MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
  98. MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
  99. MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
  100. MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
  101. MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
  102. MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
  103. MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
  104. MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
  105. MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
  106. MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
  107. MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
  108. MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
  109. MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
  110. MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
  111. MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
  112. MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
  113. MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
  114. MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
  115. MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
  116. MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
  117. MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
  118. MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
  119. MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
  120. MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
  121. MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
  122. MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
  123. MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
  124. MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
  125. };
  126. static DEFINE_MUTEX(ar8xxx_dev_list_lock);
  127. static LIST_HEAD(ar8xxx_dev_list);
  128. /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
  129. static int
  130. ar8xxx_phy_poll_reset(struct mii_bus *bus)
  131. {
  132. unsigned int sleep_msecs = 20;
  133. int ret, elapsed, i;
  134. for (elapsed = sleep_msecs; elapsed <= 600;
  135. elapsed += sleep_msecs) {
  136. msleep(sleep_msecs);
  137. for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
  138. ret = mdiobus_read(bus, i, MII_BMCR);
  139. if (ret < 0)
  140. return ret;
  141. if (ret & BMCR_RESET)
  142. break;
  143. if (i == AR8XXX_NUM_PHYS - 1) {
  144. usleep_range(1000, 2000);
  145. return 0;
  146. }
  147. }
  148. }
  149. return -ETIMEDOUT;
  150. }
  151. static int
  152. ar8xxx_phy_check_aneg(struct phy_device *phydev)
  153. {
  154. int ret;
  155. if (phydev->autoneg != AUTONEG_ENABLE)
  156. return 0;
  157. /*
  158. * BMCR_ANENABLE might have been cleared
  159. * by phy_init_hw in certain kernel versions
  160. * therefore check for it
  161. */
  162. ret = phy_read(phydev, MII_BMCR);
  163. if (ret < 0)
  164. return ret;
  165. if (ret & BMCR_ANENABLE)
  166. return 0;
  167. dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
  168. ret |= BMCR_ANENABLE | BMCR_ANRESTART;
  169. return phy_write(phydev, MII_BMCR, ret);
  170. }
  171. void
  172. ar8xxx_phy_init(struct ar8xxx_priv *priv)
  173. {
  174. int i;
  175. struct mii_bus *bus;
  176. bus = priv->mii_bus;
  177. for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
  178. if (priv->chip->phy_fixup)
  179. priv->chip->phy_fixup(priv, i);
  180. /* initialize the port itself */
  181. mdiobus_write(bus, i, MII_ADVERTISE,
  182. ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  183. if (ar8xxx_has_gige(priv))
  184. mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
  185. mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
  186. }
  187. ar8xxx_phy_poll_reset(bus);
  188. }
  189. u32
  190. ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
  191. {
  192. struct mii_bus *bus = priv->mii_bus;
  193. u16 lo, hi;
  194. lo = bus->read(bus, phy_id, regnum);
  195. hi = bus->read(bus, phy_id, regnum + 1);
  196. return (hi << 16) | lo;
  197. }
  198. void
  199. ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
  200. {
  201. struct mii_bus *bus = priv->mii_bus;
  202. u16 lo, hi;
  203. lo = val & 0xffff;
  204. hi = (u16) (val >> 16);
  205. if (priv->chip->mii_lo_first)
  206. {
  207. bus->write(bus, phy_id, regnum, lo);
  208. bus->write(bus, phy_id, regnum + 1, hi);
  209. } else {
  210. bus->write(bus, phy_id, regnum + 1, hi);
  211. bus->write(bus, phy_id, regnum, lo);
  212. }
  213. }
  214. u32
  215. ar8xxx_read(struct ar8xxx_priv *priv, int reg)
  216. {
  217. struct mii_bus *bus = priv->mii_bus;
  218. u16 r1, r2, page;
  219. u32 val;
  220. split_addr((u32) reg, &r1, &r2, &page);
  221. mutex_lock(&bus->mdio_lock);
  222. bus->write(bus, 0x18, 0, page);
  223. wait_for_page_switch();
  224. val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
  225. mutex_unlock(&bus->mdio_lock);
  226. return val;
  227. }
  228. void
  229. ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
  230. {
  231. struct mii_bus *bus = priv->mii_bus;
  232. u16 r1, r2, page;
  233. split_addr((u32) reg, &r1, &r2, &page);
  234. mutex_lock(&bus->mdio_lock);
  235. bus->write(bus, 0x18, 0, page);
  236. wait_for_page_switch();
  237. ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
  238. mutex_unlock(&bus->mdio_lock);
  239. }
  240. u32
  241. ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
  242. {
  243. struct mii_bus *bus = priv->mii_bus;
  244. u16 r1, r2, page;
  245. u32 ret;
  246. split_addr((u32) reg, &r1, &r2, &page);
  247. mutex_lock(&bus->mdio_lock);
  248. bus->write(bus, 0x18, 0, page);
  249. wait_for_page_switch();
  250. ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
  251. ret &= ~mask;
  252. ret |= val;
  253. ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
  254. mutex_unlock(&bus->mdio_lock);
  255. return ret;
  256. }
  257. void
  258. ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
  259. u16 dbg_addr, u16 dbg_data)
  260. {
  261. struct mii_bus *bus = priv->mii_bus;
  262. mutex_lock(&bus->mdio_lock);
  263. bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
  264. bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
  265. mutex_unlock(&bus->mdio_lock);
  266. }
  267. static inline void
  268. ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
  269. {
  270. bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
  271. bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
  272. bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
  273. }
  274. void
  275. ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
  276. {
  277. struct mii_bus *bus = priv->mii_bus;
  278. mutex_lock(&bus->mdio_lock);
  279. ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
  280. bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
  281. mutex_unlock(&bus->mdio_lock);
  282. }
  283. u16
  284. ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
  285. {
  286. struct mii_bus *bus = priv->mii_bus;
  287. u16 data;
  288. mutex_lock(&bus->mdio_lock);
  289. ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
  290. data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
  291. mutex_unlock(&bus->mdio_lock);
  292. return data;
  293. }
  294. static int
  295. ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
  296. unsigned timeout)
  297. {
  298. int i;
  299. for (i = 0; i < timeout; i++) {
  300. u32 t;
  301. t = ar8xxx_read(priv, reg);
  302. if ((t & mask) == val)
  303. return 0;
  304. usleep_range(1000, 2000);
  305. }
  306. return -ETIMEDOUT;
  307. }
  308. static int
  309. ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
  310. {
  311. unsigned mib_func = priv->chip->mib_func;
  312. int ret;
  313. lockdep_assert_held(&priv->mib_lock);
  314. /* Capture the hardware statistics for all ports */
  315. ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
  316. /* Wait for the capturing to complete. */
  317. ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
  318. if (ret)
  319. goto out;
  320. ret = 0;
  321. out:
  322. return ret;
  323. }
  324. static int
  325. ar8xxx_mib_capture(struct ar8xxx_priv *priv)
  326. {
  327. return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
  328. }
  329. static int
  330. ar8xxx_mib_flush(struct ar8xxx_priv *priv)
  331. {
  332. return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
  333. }
  334. static void
  335. ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
  336. {
  337. unsigned int base;
  338. u64 *mib_stats;
  339. int i;
  340. WARN_ON(port >= priv->dev.ports);
  341. lockdep_assert_held(&priv->mib_lock);
  342. base = priv->chip->reg_port_stats_start +
  343. priv->chip->reg_port_stats_length * port;
  344. mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
  345. for (i = 0; i < priv->chip->num_mibs; i++) {
  346. const struct ar8xxx_mib_desc *mib;
  347. u64 t;
  348. mib = &priv->chip->mib_decs[i];
  349. t = ar8xxx_read(priv, base + mib->offset);
  350. if (mib->size == 2) {
  351. u64 hi;
  352. hi = ar8xxx_read(priv, base + mib->offset + 4);
  353. t |= hi << 32;
  354. }
  355. if (flush)
  356. mib_stats[i] = 0;
  357. else
  358. mib_stats[i] += t;
  359. }
  360. }
  361. static void
  362. ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
  363. struct switch_port_link *link)
  364. {
  365. u32 status;
  366. u32 speed;
  367. memset(link, '\0', sizeof(*link));
  368. status = priv->chip->read_port_status(priv, port);
  369. link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
  370. if (link->aneg) {
  371. link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
  372. } else {
  373. link->link = true;
  374. if (priv->get_port_link) {
  375. int err;
  376. err = priv->get_port_link(port);
  377. if (err >= 0)
  378. link->link = !!err;
  379. }
  380. }
  381. if (!link->link)
  382. return;
  383. link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
  384. link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
  385. link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
  386. if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
  387. link->eee = priv->chip->read_port_eee_status(priv, port);
  388. speed = (status & AR8216_PORT_STATUS_SPEED) >>
  389. AR8216_PORT_STATUS_SPEED_S;
  390. switch (speed) {
  391. case AR8216_PORT_SPEED_10M:
  392. link->speed = SWITCH_PORT_SPEED_10;
  393. break;
  394. case AR8216_PORT_SPEED_100M:
  395. link->speed = SWITCH_PORT_SPEED_100;
  396. break;
  397. case AR8216_PORT_SPEED_1000M:
  398. link->speed = SWITCH_PORT_SPEED_1000;
  399. break;
  400. default:
  401. link->speed = SWITCH_PORT_SPEED_UNKNOWN;
  402. break;
  403. }
  404. }
  405. static struct sk_buff *
  406. ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
  407. {
  408. struct ar8xxx_priv *priv = dev->phy_ptr;
  409. unsigned char *buf;
  410. if (unlikely(!priv))
  411. goto error;
  412. if (!priv->vlan)
  413. goto send;
  414. if (unlikely(skb_headroom(skb) < 2)) {
  415. if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
  416. goto error;
  417. }
  418. buf = skb_push(skb, 2);
  419. buf[0] = 0x10;
  420. buf[1] = 0x80;
  421. send:
  422. return skb;
  423. error:
  424. dev_kfree_skb_any(skb);
  425. return NULL;
  426. }
  427. static void
  428. ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
  429. {
  430. struct ar8xxx_priv *priv;
  431. unsigned char *buf;
  432. int port, vlan;
  433. priv = dev->phy_ptr;
  434. if (!priv)
  435. return;
  436. /* don't strip the header if vlan mode is disabled */
  437. if (!priv->vlan)
  438. return;
  439. /* strip header, get vlan id */
  440. buf = skb->data;
  441. skb_pull(skb, 2);
  442. /* check for vlan header presence */
  443. if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
  444. return;
  445. port = buf[0] & 0x7;
  446. /* no need to fix up packets coming from a tagged source */
  447. if (priv->vlan_tagged & (1 << port))
  448. return;
  449. /* lookup port vid from local table, the switch passes an invalid vlan id */
  450. vlan = priv->vlan_id[priv->pvid[port]];
  451. buf[14 + 2] &= 0xf0;
  452. buf[14 + 2] |= vlan >> 8;
  453. buf[15 + 2] = vlan & 0xff;
  454. }
  455. int
  456. ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
  457. {
  458. int timeout = 20;
  459. u32 t = 0;
  460. while (1) {
  461. t = ar8xxx_read(priv, reg);
  462. if ((t & mask) == val)
  463. return 0;
  464. if (timeout-- <= 0)
  465. break;
  466. udelay(10);
  467. }
  468. pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
  469. (unsigned int) reg, t, mask, val);
  470. return -ETIMEDOUT;
  471. }
  472. static void
  473. ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
  474. {
  475. if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
  476. return;
  477. if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
  478. val &= AR8216_VTUDATA_MEMBER;
  479. val |= AR8216_VTUDATA_VALID;
  480. ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
  481. }
  482. op |= AR8216_VTU_ACTIVE;
  483. ar8xxx_write(priv, AR8216_REG_VTU, op);
  484. }
  485. static void
  486. ar8216_vtu_flush(struct ar8xxx_priv *priv)
  487. {
  488. ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
  489. }
  490. static void
  491. ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
  492. {
  493. u32 op;
  494. op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
  495. ar8216_vtu_op(priv, op, port_mask);
  496. }
  497. static int
  498. ar8216_atu_flush(struct ar8xxx_priv *priv)
  499. {
  500. int ret;
  501. ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
  502. if (!ret)
  503. ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
  504. AR8216_ATU_ACTIVE);
  505. return ret;
  506. }
  507. static int
  508. ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
  509. {
  510. u32 t;
  511. int ret;
  512. ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
  513. if (!ret) {
  514. t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
  515. t |= AR8216_ATU_ACTIVE;
  516. ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
  517. }
  518. return ret;
  519. }
  520. static u32
  521. ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
  522. {
  523. return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
  524. }
  525. static void
  526. ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
  527. {
  528. u32 header;
  529. u32 egress, ingress;
  530. u32 pvid;
  531. if (priv->vlan) {
  532. pvid = priv->vlan_id[priv->pvid[port]];
  533. if (priv->vlan_tagged & (1 << port))
  534. egress = AR8216_OUT_ADD_VLAN;
  535. else
  536. egress = AR8216_OUT_STRIP_VLAN;
  537. ingress = AR8216_IN_SECURE;
  538. } else {
  539. pvid = port;
  540. egress = AR8216_OUT_KEEP;
  541. ingress = AR8216_IN_PORT_ONLY;
  542. }
  543. if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
  544. header = AR8216_PORT_CTRL_HEADER;
  545. else
  546. header = 0;
  547. ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  548. AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
  549. AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
  550. AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
  551. AR8216_PORT_CTRL_LEARN | header |
  552. (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
  553. (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
  554. ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
  555. AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
  556. AR8216_PORT_VLAN_DEFAULT_ID,
  557. (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
  558. (ingress << AR8216_PORT_VLAN_MODE_S) |
  559. (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
  560. }
  561. static int
  562. ar8216_hw_init(struct ar8xxx_priv *priv)
  563. {
  564. if (priv->initialized)
  565. return 0;
  566. ar8xxx_phy_init(priv);
  567. priv->initialized = true;
  568. return 0;
  569. }
  570. static void
  571. ar8216_init_globals(struct ar8xxx_priv *priv)
  572. {
  573. /* standard atheros magic */
  574. ar8xxx_write(priv, 0x38, 0xc000050e);
  575. ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
  576. AR8216_GCTRL_MTU, 1518 + 8 + 2);
  577. }
  578. static void
  579. ar8216_init_port(struct ar8xxx_priv *priv, int port)
  580. {
  581. /* Enable port learning and tx */
  582. ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
  583. AR8216_PORT_CTRL_LEARN |
  584. (4 << AR8216_PORT_CTRL_STATE_S));
  585. ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
  586. if (port == AR8216_PORT_CPU) {
  587. ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
  588. AR8216_PORT_STATUS_LINK_UP |
  589. (ar8xxx_has_gige(priv) ?
  590. AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
  591. AR8216_PORT_STATUS_TXMAC |
  592. AR8216_PORT_STATUS_RXMAC |
  593. (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
  594. (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
  595. AR8216_PORT_STATUS_DUPLEX);
  596. } else {
  597. ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
  598. AR8216_PORT_STATUS_LINK_AUTO);
  599. }
  600. }
  601. static void
  602. ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
  603. {
  604. int timeout = 20;
  605. while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout)
  606. udelay(10);
  607. if (!timeout)
  608. pr_err("ar8216: timeout waiting for atu to become ready\n");
  609. }
  610. static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
  611. struct arl_entry *a, u32 *status, enum arl_op op)
  612. {
  613. struct mii_bus *bus = priv->mii_bus;
  614. u16 r2, page;
  615. u16 r1_func0, r1_func1, r1_func2;
  616. u32 t, val0, val1, val2;
  617. int i;
  618. split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
  619. r2 |= 0x10;
  620. r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
  621. r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
  622. switch (op) {
  623. case AR8XXX_ARL_INITIALIZE:
  624. /* all ATU registers are on the same page
  625. * therefore set page only once
  626. */
  627. bus->write(bus, 0x18, 0, page);
  628. wait_for_page_switch();
  629. ar8216_wait_atu_ready(priv, r2, r1_func0);
  630. ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
  631. ar8xxx_mii_write32(priv, r2, r1_func1, 0);
  632. ar8xxx_mii_write32(priv, r2, r1_func2, 0);
  633. break;
  634. case AR8XXX_ARL_GET_NEXT:
  635. t = ar8xxx_mii_read32(priv, r2, r1_func0);
  636. t |= AR8216_ATU_ACTIVE;
  637. ar8xxx_mii_write32(priv, r2, r1_func0, t);
  638. ar8216_wait_atu_ready(priv, r2, r1_func0);
  639. val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
  640. val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
  641. val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
  642. *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
  643. if (!*status)
  644. break;
  645. i = 0;
  646. t = AR8216_ATU_PORT0;
  647. while (!(val2 & t) && ++i < priv->dev.ports)
  648. t <<= 1;
  649. a->port = i;
  650. a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
  651. a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
  652. a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
  653. a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
  654. a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
  655. a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
  656. break;
  657. }
  658. }
  659. static void
  660. ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
  661. {
  662. u32 egress, ingress;
  663. u32 pvid;
  664. if (priv->vlan) {
  665. pvid = priv->vlan_id[priv->pvid[port]];
  666. if (priv->vlan_tagged & (1 << port))
  667. egress = AR8216_OUT_ADD_VLAN;
  668. else
  669. egress = AR8216_OUT_STRIP_VLAN;
  670. ingress = AR8216_IN_SECURE;
  671. } else {
  672. pvid = port;
  673. egress = AR8216_OUT_KEEP;
  674. ingress = AR8216_IN_PORT_ONLY;
  675. }
  676. ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
  677. AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
  678. AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
  679. AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
  680. AR8216_PORT_CTRL_LEARN |
  681. (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
  682. (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
  683. ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
  684. AR8236_PORT_VLAN_DEFAULT_ID,
  685. (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
  686. ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
  687. AR8236_PORT_VLAN2_VLAN_MODE |
  688. AR8236_PORT_VLAN2_MEMBER,
  689. (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
  690. (members << AR8236_PORT_VLAN2_MEMBER_S));
  691. }
  692. static void
  693. ar8236_init_globals(struct ar8xxx_priv *priv)
  694. {
  695. /* enable jumbo frames */
  696. ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
  697. AR8316_GCTRL_MTU, 9018 + 8 + 2);
  698. /* enable cpu port to receive arp frames */
  699. ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
  700. AR8236_ATU_CTRL_RES);
  701. /* enable cpu port to receive multicast and broadcast frames */
  702. ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
  703. AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
  704. /* Enable MIB counters */
  705. ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
  706. (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
  707. AR8236_MIB_EN);
  708. }
  709. static int
  710. ar8316_hw_init(struct ar8xxx_priv *priv)
  711. {
  712. u32 val, newval;
  713. val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
  714. if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
  715. if (priv->port4_phy) {
  716. /* value taken from Ubiquiti RouterStation Pro */
  717. newval = 0x81461bea;
  718. pr_info("ar8316: Using port 4 as PHY\n");
  719. } else {
  720. newval = 0x01261be2;
  721. pr_info("ar8316: Using port 4 as switch port\n");
  722. }
  723. } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
  724. /* value taken from AVM Fritz!Box 7390 sources */
  725. newval = 0x010e5b71;
  726. } else {
  727. /* no known value for phy interface */
  728. pr_err("ar8316: unsupported mii mode: %d.\n",
  729. priv->phy->interface);
  730. return -EINVAL;
  731. }
  732. if (val == newval)
  733. goto out;
  734. ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
  735. if (priv->port4_phy &&
  736. priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
  737. /* work around for phy4 rgmii mode */
  738. ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
  739. /* rx delay */
  740. ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
  741. /* tx delay */
  742. ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
  743. msleep(1000);
  744. }
  745. ar8xxx_phy_init(priv);
  746. out:
  747. priv->initialized = true;
  748. return 0;
  749. }
  750. static void
  751. ar8316_init_globals(struct ar8xxx_priv *priv)
  752. {
  753. /* standard atheros magic */
  754. ar8xxx_write(priv, 0x38, 0xc000050e);
  755. /* enable cpu port to receive multicast and broadcast frames */
  756. ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
  757. /* enable jumbo frames */
  758. ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
  759. AR8316_GCTRL_MTU, 9018 + 8 + 2);
  760. /* Enable MIB counters */
  761. ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
  762. (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
  763. AR8236_MIB_EN);
  764. }
  765. int
  766. ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
  767. struct switch_val *val)
  768. {
  769. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  770. priv->vlan = !!val->value.i;
  771. return 0;
  772. }
  773. int
  774. ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
  775. struct switch_val *val)
  776. {
  777. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  778. val->value.i = priv->vlan;
  779. return 0;
  780. }
  781. int
  782. ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
  783. {
  784. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  785. /* make sure no invalid PVIDs get set */
  786. if (vlan < 0 || vlan >= dev->vlans ||
  787. port < 0 || port >= AR8X16_MAX_PORTS)
  788. return -EINVAL;
  789. priv->pvid[port] = vlan;
  790. return 0;
  791. }
  792. int
  793. ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
  794. {
  795. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  796. if (port < 0 || port >= AR8X16_MAX_PORTS)
  797. return -EINVAL;
  798. *vlan = priv->pvid[port];
  799. return 0;
  800. }
  801. static int
  802. ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
  803. struct switch_val *val)
  804. {
  805. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  806. if (val->port_vlan >= AR8X16_MAX_VLANS)
  807. return -EINVAL;
  808. priv->vlan_id[val->port_vlan] = val->value.i;
  809. return 0;
  810. }
  811. static int
  812. ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
  813. struct switch_val *val)
  814. {
  815. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  816. val->value.i = priv->vlan_id[val->port_vlan];
  817. return 0;
  818. }
  819. int
  820. ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
  821. struct switch_port_link *link)
  822. {
  823. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  824. ar8216_read_port_link(priv, port, link);
  825. return 0;
  826. }
  827. static int
  828. ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
  829. {
  830. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  831. u8 ports;
  832. int i;
  833. if (val->port_vlan >= AR8X16_MAX_VLANS)
  834. return -EINVAL;
  835. ports = priv->vlan_table[val->port_vlan];
  836. val->len = 0;
  837. for (i = 0; i < dev->ports; i++) {
  838. struct switch_port *p;
  839. if (!(ports & (1 << i)))
  840. continue;
  841. p = &val->value.ports[val->len++];
  842. p->id = i;
  843. if (priv->vlan_tagged & (1 << i))
  844. p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
  845. else
  846. p->flags = 0;
  847. }
  848. return 0;
  849. }
  850. static int
  851. ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
  852. {
  853. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  854. u8 *vt = &priv->vlan_table[val->port_vlan];
  855. int i, j;
  856. *vt = 0;
  857. for (i = 0; i < val->len; i++) {
  858. struct switch_port *p = &val->value.ports[i];
  859. if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
  860. priv->vlan_tagged |= (1 << p->id);
  861. } else {
  862. priv->vlan_tagged &= ~(1 << p->id);
  863. priv->pvid[p->id] = val->port_vlan;
  864. /* make sure that an untagged port does not
  865. * appear in other vlans */
  866. for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  867. if (j == val->port_vlan)
  868. continue;
  869. priv->vlan_table[j] &= ~(1 << p->id);
  870. }
  871. }
  872. *vt |= 1 << p->id;
  873. }
  874. return 0;
  875. }
  876. static void
  877. ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
  878. {
  879. int port;
  880. /* reset all mirror registers */
  881. ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
  882. AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
  883. (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
  884. for (port = 0; port < AR8216_NUM_PORTS; port++) {
  885. ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
  886. AR8216_PORT_CTRL_MIRROR_RX);
  887. ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
  888. AR8216_PORT_CTRL_MIRROR_TX);
  889. }
  890. /* now enable mirroring if necessary */
  891. if (priv->source_port >= AR8216_NUM_PORTS ||
  892. priv->monitor_port >= AR8216_NUM_PORTS ||
  893. priv->source_port == priv->monitor_port) {
  894. return;
  895. }
  896. ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
  897. AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
  898. (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
  899. if (priv->mirror_rx)
  900. ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
  901. AR8216_PORT_CTRL_MIRROR_RX);
  902. if (priv->mirror_tx)
  903. ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
  904. AR8216_PORT_CTRL_MIRROR_TX);
  905. }
  906. static inline u32
  907. ar8xxx_age_time_val(int age_time)
  908. {
  909. return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
  910. AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
  911. }
  912. static inline void
  913. ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
  914. {
  915. u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
  916. ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
  917. }
  918. int
  919. ar8xxx_sw_hw_apply(struct switch_dev *dev)
  920. {
  921. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  922. const struct ar8xxx_chip *chip = priv->chip;
  923. u8 portmask[AR8X16_MAX_PORTS];
  924. int i, j;
  925. mutex_lock(&priv->reg_mutex);
  926. /* flush all vlan translation unit entries */
  927. priv->chip->vtu_flush(priv);
  928. memset(portmask, 0, sizeof(portmask));
  929. if (!priv->init) {
  930. /* calculate the port destination masks and load vlans
  931. * into the vlan translation unit */
  932. for (j = 0; j < AR8X16_MAX_VLANS; j++) {
  933. u8 vp = priv->vlan_table[j];
  934. if (!vp)
  935. continue;
  936. for (i = 0; i < dev->ports; i++) {
  937. u8 mask = (1 << i);
  938. if (vp & mask)
  939. portmask[i] |= vp & ~mask;
  940. }
  941. chip->vtu_load_vlan(priv, priv->vlan_id[j],
  942. priv->vlan_table[j]);
  943. }
  944. } else {
  945. /* vlan disabled:
  946. * isolate all ports, but connect them to the cpu port */
  947. for (i = 0; i < dev->ports; i++) {
  948. if (i == AR8216_PORT_CPU)
  949. continue;
  950. portmask[i] = 1 << AR8216_PORT_CPU;
  951. portmask[AR8216_PORT_CPU] |= (1 << i);
  952. }
  953. }
  954. /* update the port destination mask registers and tag settings */
  955. for (i = 0; i < dev->ports; i++) {
  956. chip->setup_port(priv, i, portmask[i]);
  957. }
  958. chip->set_mirror_regs(priv);
  959. /* set age time */
  960. if (chip->reg_arl_ctrl)
  961. ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
  962. mutex_unlock(&priv->reg_mutex);
  963. return 0;
  964. }
  965. int
  966. ar8xxx_sw_reset_switch(struct switch_dev *dev)
  967. {
  968. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  969. const struct ar8xxx_chip *chip = priv->chip;
  970. int i;
  971. mutex_lock(&priv->reg_mutex);
  972. memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
  973. offsetof(struct ar8xxx_priv, vlan));
  974. for (i = 0; i < AR8X16_MAX_VLANS; i++)
  975. priv->vlan_id[i] = i;
  976. /* Configure all ports */
  977. for (i = 0; i < dev->ports; i++)
  978. chip->init_port(priv, i);
  979. priv->mirror_rx = false;
  980. priv->mirror_tx = false;
  981. priv->source_port = 0;
  982. priv->monitor_port = 0;
  983. priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
  984. chip->init_globals(priv);
  985. chip->atu_flush(priv);
  986. mutex_unlock(&priv->reg_mutex);
  987. return chip->sw_hw_apply(dev);
  988. }
  989. int
  990. ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
  991. const struct switch_attr *attr,
  992. struct switch_val *val)
  993. {
  994. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  995. unsigned int len;
  996. int ret;
  997. if (!ar8xxx_has_mib_counters(priv))
  998. return -EOPNOTSUPP;
  999. mutex_lock(&priv->mib_lock);
  1000. len = priv->dev.ports * priv->chip->num_mibs *
  1001. sizeof(*priv->mib_stats);
  1002. memset(priv->mib_stats, '\0', len);
  1003. ret = ar8xxx_mib_flush(priv);
  1004. if (ret)
  1005. goto unlock;
  1006. ret = 0;
  1007. unlock:
  1008. mutex_unlock(&priv->mib_lock);
  1009. return ret;
  1010. }
  1011. int
  1012. ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
  1013. const struct switch_attr *attr,
  1014. struct switch_val *val)
  1015. {
  1016. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1017. mutex_lock(&priv->reg_mutex);
  1018. priv->mirror_rx = !!val->value.i;
  1019. priv->chip->set_mirror_regs(priv);
  1020. mutex_unlock(&priv->reg_mutex);
  1021. return 0;
  1022. }
  1023. int
  1024. ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
  1025. const struct switch_attr *attr,
  1026. struct switch_val *val)
  1027. {
  1028. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1029. val->value.i = priv->mirror_rx;
  1030. return 0;
  1031. }
  1032. int
  1033. ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
  1034. const struct switch_attr *attr,
  1035. struct switch_val *val)
  1036. {
  1037. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1038. mutex_lock(&priv->reg_mutex);
  1039. priv->mirror_tx = !!val->value.i;
  1040. priv->chip->set_mirror_regs(priv);
  1041. mutex_unlock(&priv->reg_mutex);
  1042. return 0;
  1043. }
  1044. int
  1045. ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
  1046. const struct switch_attr *attr,
  1047. struct switch_val *val)
  1048. {
  1049. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1050. val->value.i = priv->mirror_tx;
  1051. return 0;
  1052. }
  1053. int
  1054. ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
  1055. const struct switch_attr *attr,
  1056. struct switch_val *val)
  1057. {
  1058. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1059. mutex_lock(&priv->reg_mutex);
  1060. priv->monitor_port = val->value.i;
  1061. priv->chip->set_mirror_regs(priv);
  1062. mutex_unlock(&priv->reg_mutex);
  1063. return 0;
  1064. }
  1065. int
  1066. ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
  1067. const struct switch_attr *attr,
  1068. struct switch_val *val)
  1069. {
  1070. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1071. val->value.i = priv->monitor_port;
  1072. return 0;
  1073. }
  1074. int
  1075. ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
  1076. const struct switch_attr *attr,
  1077. struct switch_val *val)
  1078. {
  1079. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1080. mutex_lock(&priv->reg_mutex);
  1081. priv->source_port = val->value.i;
  1082. priv->chip->set_mirror_regs(priv);
  1083. mutex_unlock(&priv->reg_mutex);
  1084. return 0;
  1085. }
  1086. int
  1087. ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
  1088. const struct switch_attr *attr,
  1089. struct switch_val *val)
  1090. {
  1091. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1092. val->value.i = priv->source_port;
  1093. return 0;
  1094. }
  1095. int
  1096. ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
  1097. const struct switch_attr *attr,
  1098. struct switch_val *val)
  1099. {
  1100. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1101. int port;
  1102. int ret;
  1103. if (!ar8xxx_has_mib_counters(priv))
  1104. return -EOPNOTSUPP;
  1105. port = val->port_vlan;
  1106. if (port >= dev->ports)
  1107. return -EINVAL;
  1108. mutex_lock(&priv->mib_lock);
  1109. ret = ar8xxx_mib_capture(priv);
  1110. if (ret)
  1111. goto unlock;
  1112. ar8xxx_mib_fetch_port_stat(priv, port, true);
  1113. ret = 0;
  1114. unlock:
  1115. mutex_unlock(&priv->mib_lock);
  1116. return ret;
  1117. }
  1118. static void
  1119. ar8xxx_byte_to_str(char *buf, int len, u64 byte)
  1120. {
  1121. unsigned long b;
  1122. const char *unit;
  1123. if (byte >= 0x40000000) { /* 1 GiB */
  1124. b = byte * 10 / 0x40000000;
  1125. unit = "GiB";
  1126. } else if (byte >= 0x100000) { /* 1 MiB */
  1127. b = byte * 10 / 0x100000;
  1128. unit = "MiB";
  1129. } else if (byte >= 0x400) { /* 1 KiB */
  1130. b = byte * 10 / 0x400;
  1131. unit = "KiB";
  1132. } else {
  1133. b = byte;
  1134. unit = "Byte";
  1135. }
  1136. if (strcmp(unit, "Byte"))
  1137. snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
  1138. else
  1139. snprintf(buf, len, "%lu %s", b, unit);
  1140. }
  1141. int
  1142. ar8xxx_sw_get_port_mib(struct switch_dev *dev,
  1143. const struct switch_attr *attr,
  1144. struct switch_val *val)
  1145. {
  1146. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1147. const struct ar8xxx_chip *chip = priv->chip;
  1148. u64 *mib_stats, mib_data;
  1149. unsigned int port;
  1150. int ret;
  1151. char *buf = priv->buf;
  1152. char buf1[64];
  1153. const char *mib_name;
  1154. int i, len = 0;
  1155. bool mib_stats_empty = true;
  1156. if (!ar8xxx_has_mib_counters(priv))
  1157. return -EOPNOTSUPP;
  1158. port = val->port_vlan;
  1159. if (port >= dev->ports)
  1160. return -EINVAL;
  1161. mutex_lock(&priv->mib_lock);
  1162. ret = ar8xxx_mib_capture(priv);
  1163. if (ret)
  1164. goto unlock;
  1165. ar8xxx_mib_fetch_port_stat(priv, port, false);
  1166. len += snprintf(buf + len, sizeof(priv->buf) - len,
  1167. "MIB counters\n");
  1168. mib_stats = &priv->mib_stats[port * chip->num_mibs];
  1169. for (i = 0; i < chip->num_mibs; i++) {
  1170. mib_name = chip->mib_decs[i].name;
  1171. mib_data = mib_stats[i];
  1172. len += snprintf(buf + len, sizeof(priv->buf) - len,
  1173. "%-12s: %llu\n", mib_name, mib_data);
  1174. if ((!strcmp(mib_name, "TxByte") ||
  1175. !strcmp(mib_name, "RxGoodByte")) &&
  1176. mib_data >= 1024) {
  1177. ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
  1178. --len; /* discard newline at the end of buf */
  1179. len += snprintf(buf + len, sizeof(priv->buf) - len,
  1180. " (%s)\n", buf1);
  1181. }
  1182. if (mib_stats_empty && mib_data)
  1183. mib_stats_empty = false;
  1184. }
  1185. if (mib_stats_empty)
  1186. len = snprintf(buf, sizeof(priv->buf), "No MIB data");
  1187. val->value.s = buf;
  1188. val->len = len;
  1189. ret = 0;
  1190. unlock:
  1191. mutex_unlock(&priv->mib_lock);
  1192. return ret;
  1193. }
  1194. int
  1195. ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
  1196. struct switch_val *val)
  1197. {
  1198. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1199. int age_time = val->value.i;
  1200. u32 age_time_val;
  1201. if (age_time < 0)
  1202. return -EINVAL;
  1203. age_time_val = ar8xxx_age_time_val(age_time);
  1204. if (age_time_val == 0 || age_time_val > 0xffff)
  1205. return -EINVAL;
  1206. priv->arl_age_time = age_time;
  1207. return 0;
  1208. }
  1209. int
  1210. ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
  1211. struct switch_val *val)
  1212. {
  1213. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1214. val->value.i = priv->arl_age_time;
  1215. return 0;
  1216. }
  1217. int
  1218. ar8xxx_sw_get_arl_table(struct switch_dev *dev,
  1219. const struct switch_attr *attr,
  1220. struct switch_val *val)
  1221. {
  1222. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1223. struct mii_bus *bus = priv->mii_bus;
  1224. const struct ar8xxx_chip *chip = priv->chip;
  1225. char *buf = priv->arl_buf;
  1226. int i, j, k, len = 0;
  1227. struct arl_entry *a, *a1;
  1228. u32 status;
  1229. if (!chip->get_arl_entry)
  1230. return -EOPNOTSUPP;
  1231. mutex_lock(&priv->reg_mutex);
  1232. mutex_lock(&bus->mdio_lock);
  1233. chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
  1234. for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
  1235. a = &priv->arl_table[i];
  1236. duplicate:
  1237. chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
  1238. if (!status)
  1239. break;
  1240. /* avoid duplicates
  1241. * ARL table can include multiple valid entries
  1242. * per MAC, just with differing status codes
  1243. */
  1244. for (j = 0; j < i; ++j) {
  1245. a1 = &priv->arl_table[j];
  1246. if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac)))
  1247. goto duplicate;
  1248. }
  1249. }
  1250. mutex_unlock(&bus->mdio_lock);
  1251. len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
  1252. "address resolution table\n");
  1253. if (i == AR8XXX_NUM_ARL_RECORDS)
  1254. len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
  1255. "Too many entries found, displaying the first %d only!\n",
  1256. AR8XXX_NUM_ARL_RECORDS);
  1257. for (j = 0; j < priv->dev.ports; ++j) {
  1258. for (k = 0; k < i; ++k) {
  1259. a = &priv->arl_table[k];
  1260. if (a->port != j)
  1261. continue;
  1262. len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
  1263. "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
  1264. j,
  1265. a->mac[5], a->mac[4], a->mac[3],
  1266. a->mac[2], a->mac[1], a->mac[0]);
  1267. }
  1268. }
  1269. val->value.s = buf;
  1270. val->len = len;
  1271. mutex_unlock(&priv->reg_mutex);
  1272. return 0;
  1273. }
  1274. int
  1275. ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
  1276. const struct switch_attr *attr,
  1277. struct switch_val *val)
  1278. {
  1279. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1280. int ret;
  1281. mutex_lock(&priv->reg_mutex);
  1282. ret = priv->chip->atu_flush(priv);
  1283. mutex_unlock(&priv->reg_mutex);
  1284. return ret;
  1285. }
  1286. int
  1287. ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
  1288. const struct switch_attr *attr,
  1289. struct switch_val *val)
  1290. {
  1291. struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
  1292. int port, ret;
  1293. port = val->port_vlan;
  1294. if (port >= dev->ports)
  1295. return -EINVAL;
  1296. mutex_lock(&priv->reg_mutex);
  1297. ret = priv->chip->atu_flush_port(priv, port);
  1298. mutex_unlock(&priv->reg_mutex);
  1299. return ret;
  1300. }
  1301. static const struct switch_attr ar8xxx_sw_attr_globals[] = {
  1302. {
  1303. .type = SWITCH_TYPE_INT,
  1304. .name = "enable_vlan",
  1305. .description = "Enable VLAN mode",
  1306. .set = ar8xxx_sw_set_vlan,
  1307. .get = ar8xxx_sw_get_vlan,
  1308. .max = 1
  1309. },
  1310. {
  1311. .type = SWITCH_TYPE_NOVAL,
  1312. .name = "reset_mibs",
  1313. .description = "Reset all MIB counters",
  1314. .set = ar8xxx_sw_set_reset_mibs,
  1315. },
  1316. {
  1317. .type = SWITCH_TYPE_INT,
  1318. .name = "enable_mirror_rx",
  1319. .description = "Enable mirroring of RX packets",
  1320. .set = ar8xxx_sw_set_mirror_rx_enable,
  1321. .get = ar8xxx_sw_get_mirror_rx_enable,
  1322. .max = 1
  1323. },
  1324. {
  1325. .type = SWITCH_TYPE_INT,
  1326. .name = "enable_mirror_tx",
  1327. .description = "Enable mirroring of TX packets",
  1328. .set = ar8xxx_sw_set_mirror_tx_enable,
  1329. .get = ar8xxx_sw_get_mirror_tx_enable,
  1330. .max = 1
  1331. },
  1332. {
  1333. .type = SWITCH_TYPE_INT,
  1334. .name = "mirror_monitor_port",
  1335. .description = "Mirror monitor port",
  1336. .set = ar8xxx_sw_set_mirror_monitor_port,
  1337. .get = ar8xxx_sw_get_mirror_monitor_port,
  1338. .max = AR8216_NUM_PORTS - 1
  1339. },
  1340. {
  1341. .type = SWITCH_TYPE_INT,
  1342. .name = "mirror_source_port",
  1343. .description = "Mirror source port",
  1344. .set = ar8xxx_sw_set_mirror_source_port,
  1345. .get = ar8xxx_sw_get_mirror_source_port,
  1346. .max = AR8216_NUM_PORTS - 1
  1347. },
  1348. {
  1349. .type = SWITCH_TYPE_STRING,
  1350. .name = "arl_table",
  1351. .description = "Get ARL table",
  1352. .set = NULL,
  1353. .get = ar8xxx_sw_get_arl_table,
  1354. },
  1355. {
  1356. .type = SWITCH_TYPE_NOVAL,
  1357. .name = "flush_arl_table",
  1358. .description = "Flush ARL table",
  1359. .set = ar8xxx_sw_set_flush_arl_table,
  1360. },
  1361. };
  1362. const struct switch_attr ar8xxx_sw_attr_port[] = {
  1363. {
  1364. .type = SWITCH_TYPE_NOVAL,
  1365. .name = "reset_mib",
  1366. .description = "Reset single port MIB counters",
  1367. .set = ar8xxx_sw_set_port_reset_mib,
  1368. },
  1369. {
  1370. .type = SWITCH_TYPE_STRING,
  1371. .name = "mib",
  1372. .description = "Get port's MIB counters",
  1373. .set = NULL,
  1374. .get = ar8xxx_sw_get_port_mib,
  1375. },
  1376. {
  1377. .type = SWITCH_TYPE_NOVAL,
  1378. .name = "flush_arl_table",
  1379. .description = "Flush port's ARL table entries",
  1380. .set = ar8xxx_sw_set_flush_port_arl_table,
  1381. },
  1382. };
  1383. const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
  1384. {
  1385. .type = SWITCH_TYPE_INT,
  1386. .name = "vid",
  1387. .description = "VLAN ID (0-4094)",
  1388. .set = ar8xxx_sw_set_vid,
  1389. .get = ar8xxx_sw_get_vid,
  1390. .max = 4094,
  1391. },
  1392. };
  1393. static const struct switch_dev_ops ar8xxx_sw_ops = {
  1394. .attr_global = {
  1395. .attr = ar8xxx_sw_attr_globals,
  1396. .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
  1397. },
  1398. .attr_port = {
  1399. .attr = ar8xxx_sw_attr_port,
  1400. .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
  1401. },
  1402. .attr_vlan = {
  1403. .attr = ar8xxx_sw_attr_vlan,
  1404. .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
  1405. },
  1406. .get_port_pvid = ar8xxx_sw_get_pvid,
  1407. .set_port_pvid = ar8xxx_sw_set_pvid,
  1408. .get_vlan_ports = ar8xxx_sw_get_ports,
  1409. .set_vlan_ports = ar8xxx_sw_set_ports,
  1410. .apply_config = ar8xxx_sw_hw_apply,
  1411. .reset_switch = ar8xxx_sw_reset_switch,
  1412. .get_port_link = ar8xxx_sw_get_port_link,
  1413. };
  1414. static const struct ar8xxx_chip ar8216_chip = {
  1415. .caps = AR8XXX_CAP_MIB_COUNTERS,
  1416. .reg_port_stats_start = 0x19000,
  1417. .reg_port_stats_length = 0xa0,
  1418. .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
  1419. .name = "Atheros AR8216",
  1420. .ports = AR8216_NUM_PORTS,
  1421. .vlans = AR8216_NUM_VLANS,
  1422. .swops = &ar8xxx_sw_ops,
  1423. .hw_init = ar8216_hw_init,
  1424. .init_globals = ar8216_init_globals,
  1425. .init_port = ar8216_init_port,
  1426. .setup_port = ar8216_setup_port,
  1427. .read_port_status = ar8216_read_port_status,
  1428. .atu_flush = ar8216_atu_flush,
  1429. .atu_flush_port = ar8216_atu_flush_port,
  1430. .vtu_flush = ar8216_vtu_flush,
  1431. .vtu_load_vlan = ar8216_vtu_load_vlan,
  1432. .set_mirror_regs = ar8216_set_mirror_regs,
  1433. .get_arl_entry = ar8216_get_arl_entry,
  1434. .sw_hw_apply = ar8xxx_sw_hw_apply,
  1435. .num_mibs = ARRAY_SIZE(ar8216_mibs),
  1436. .mib_decs = ar8216_mibs,
  1437. .mib_func = AR8216_REG_MIB_FUNC
  1438. };
  1439. static const struct ar8xxx_chip ar8236_chip = {
  1440. .caps = AR8XXX_CAP_MIB_COUNTERS,
  1441. .reg_port_stats_start = 0x20000,
  1442. .reg_port_stats_length = 0x100,
  1443. .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
  1444. .name = "Atheros AR8236",
  1445. .ports = AR8216_NUM_PORTS,
  1446. .vlans = AR8216_NUM_VLANS,
  1447. .swops = &ar8xxx_sw_ops,
  1448. .hw_init = ar8216_hw_init,
  1449. .init_globals = ar8236_init_globals,
  1450. .init_port = ar8216_init_port,
  1451. .setup_port = ar8236_setup_port,
  1452. .read_port_status = ar8216_read_port_status,
  1453. .atu_flush = ar8216_atu_flush,
  1454. .atu_flush_port = ar8216_atu_flush_port,
  1455. .vtu_flush = ar8216_vtu_flush,
  1456. .vtu_load_vlan = ar8216_vtu_load_vlan,
  1457. .set_mirror_regs = ar8216_set_mirror_regs,
  1458. .get_arl_entry = ar8216_get_arl_entry,
  1459. .sw_hw_apply = ar8xxx_sw_hw_apply,
  1460. .num_mibs = ARRAY_SIZE(ar8236_mibs),
  1461. .mib_decs = ar8236_mibs,
  1462. .mib_func = AR8216_REG_MIB_FUNC
  1463. };
  1464. static const struct ar8xxx_chip ar8316_chip = {
  1465. .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
  1466. .reg_port_stats_start = 0x20000,
  1467. .reg_port_stats_length = 0x100,
  1468. .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
  1469. .name = "Atheros AR8316",
  1470. .ports = AR8216_NUM_PORTS,
  1471. .vlans = AR8X16_MAX_VLANS,
  1472. .swops = &ar8xxx_sw_ops,
  1473. .hw_init = ar8316_hw_init,
  1474. .init_globals = ar8316_init_globals,
  1475. .init_port = ar8216_init_port,
  1476. .setup_port = ar8216_setup_port,
  1477. .read_port_status = ar8216_read_port_status,
  1478. .atu_flush = ar8216_atu_flush,
  1479. .atu_flush_port = ar8216_atu_flush_port,
  1480. .vtu_flush = ar8216_vtu_flush,
  1481. .vtu_load_vlan = ar8216_vtu_load_vlan,
  1482. .set_mirror_regs = ar8216_set_mirror_regs,
  1483. .get_arl_entry = ar8216_get_arl_entry,
  1484. .sw_hw_apply = ar8xxx_sw_hw_apply,
  1485. .num_mibs = ARRAY_SIZE(ar8236_mibs),
  1486. .mib_decs = ar8236_mibs,
  1487. .mib_func = AR8216_REG_MIB_FUNC
  1488. };
  1489. static int
  1490. ar8xxx_id_chip(struct ar8xxx_priv *priv)
  1491. {
  1492. u32 val;
  1493. u16 id;
  1494. int i;
  1495. val = ar8xxx_read(priv, AR8216_REG_CTRL);
  1496. if (val == ~0)
  1497. return -ENODEV;
  1498. id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
  1499. for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
  1500. u16 t;
  1501. val = ar8xxx_read(priv, AR8216_REG_CTRL);
  1502. if (val == ~0)
  1503. return -ENODEV;
  1504. t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
  1505. if (t != id)
  1506. return -ENODEV;
  1507. }
  1508. priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
  1509. priv->chip_rev = (id & AR8216_CTRL_REVISION);
  1510. switch (priv->chip_ver) {
  1511. case AR8XXX_VER_AR8216:
  1512. priv->chip = &ar8216_chip;
  1513. break;
  1514. case AR8XXX_VER_AR8236:
  1515. priv->chip = &ar8236_chip;
  1516. break;
  1517. case AR8XXX_VER_AR8316:
  1518. priv->chip = &ar8316_chip;
  1519. break;
  1520. case AR8XXX_VER_AR8327:
  1521. priv->chip = &ar8327_chip;
  1522. break;
  1523. case AR8XXX_VER_AR8337:
  1524. priv->chip = &ar8337_chip;
  1525. break;
  1526. default:
  1527. pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
  1528. priv->chip_ver, priv->chip_rev);
  1529. return -ENODEV;
  1530. }
  1531. return 0;
  1532. }
  1533. static void
  1534. ar8xxx_mib_work_func(struct work_struct *work)
  1535. {
  1536. struct ar8xxx_priv *priv;
  1537. int err;
  1538. priv = container_of(work, struct ar8xxx_priv, mib_work.work);
  1539. mutex_lock(&priv->mib_lock);
  1540. err = ar8xxx_mib_capture(priv);
  1541. if (err)
  1542. goto next_port;
  1543. ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
  1544. next_port:
  1545. priv->mib_next_port++;
  1546. if (priv->mib_next_port >= priv->dev.ports)
  1547. priv->mib_next_port = 0;
  1548. mutex_unlock(&priv->mib_lock);
  1549. schedule_delayed_work(&priv->mib_work,
  1550. msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
  1551. }
  1552. static int
  1553. ar8xxx_mib_init(struct ar8xxx_priv *priv)
  1554. {
  1555. unsigned int len;
  1556. if (!ar8xxx_has_mib_counters(priv))
  1557. return 0;
  1558. BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
  1559. len = priv->dev.ports * priv->chip->num_mibs *
  1560. sizeof(*priv->mib_stats);
  1561. priv->mib_stats = kzalloc(len, GFP_KERNEL);
  1562. if (!priv->mib_stats)
  1563. return -ENOMEM;
  1564. return 0;
  1565. }
  1566. static void
  1567. ar8xxx_mib_start(struct ar8xxx_priv *priv)
  1568. {
  1569. if (!ar8xxx_has_mib_counters(priv))
  1570. return;
  1571. schedule_delayed_work(&priv->mib_work,
  1572. msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
  1573. }
  1574. static void
  1575. ar8xxx_mib_stop(struct ar8xxx_priv *priv)
  1576. {
  1577. if (!ar8xxx_has_mib_counters(priv))
  1578. return;
  1579. cancel_delayed_work_sync(&priv->mib_work);
  1580. }
  1581. static struct ar8xxx_priv *
  1582. ar8xxx_create(void)
  1583. {
  1584. struct ar8xxx_priv *priv;
  1585. priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
  1586. if (priv == NULL)
  1587. return NULL;
  1588. mutex_init(&priv->reg_mutex);
  1589. mutex_init(&priv->mib_lock);
  1590. INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
  1591. return priv;
  1592. }
  1593. static void
  1594. ar8xxx_free(struct ar8xxx_priv *priv)
  1595. {
  1596. if (priv->chip && priv->chip->cleanup)
  1597. priv->chip->cleanup(priv);
  1598. kfree(priv->chip_data);
  1599. kfree(priv->mib_stats);
  1600. kfree(priv);
  1601. }
  1602. static int
  1603. ar8xxx_probe_switch(struct ar8xxx_priv *priv)
  1604. {
  1605. const struct ar8xxx_chip *chip;
  1606. struct switch_dev *swdev;
  1607. int ret;
  1608. ret = ar8xxx_id_chip(priv);
  1609. if (ret)
  1610. return ret;
  1611. chip = priv->chip;
  1612. swdev = &priv->dev;
  1613. swdev->cpu_port = AR8216_PORT_CPU;
  1614. swdev->name = chip->name;
  1615. swdev->vlans = chip->vlans;
  1616. swdev->ports = chip->ports;
  1617. swdev->ops = chip->swops;
  1618. ret = ar8xxx_mib_init(priv);
  1619. if (ret)
  1620. return ret;
  1621. return 0;
  1622. }
  1623. static int
  1624. ar8xxx_start(struct ar8xxx_priv *priv)
  1625. {
  1626. int ret;
  1627. priv->init = true;
  1628. ret = priv->chip->hw_init(priv);
  1629. if (ret)
  1630. return ret;
  1631. ret = ar8xxx_sw_reset_switch(&priv->dev);
  1632. if (ret)
  1633. return ret;
  1634. priv->init = false;
  1635. ar8xxx_mib_start(priv);
  1636. return 0;
  1637. }
  1638. static int
  1639. ar8xxx_phy_config_init(struct phy_device *phydev)
  1640. {
  1641. struct ar8xxx_priv *priv = phydev->priv;
  1642. struct net_device *dev = phydev->attached_dev;
  1643. int ret;
  1644. if (WARN_ON(!priv))
  1645. return -ENODEV;
  1646. if (priv->chip->config_at_probe)
  1647. return ar8xxx_phy_check_aneg(phydev);
  1648. priv->phy = phydev;
  1649. if (phydev->addr != 0) {
  1650. if (chip_is_ar8316(priv)) {
  1651. /* switch device has been initialized, reinit */
  1652. priv->dev.ports = (AR8216_NUM_PORTS - 1);
  1653. priv->initialized = false;
  1654. priv->port4_phy = true;
  1655. ar8316_hw_init(priv);
  1656. return 0;
  1657. }
  1658. return 0;
  1659. }
  1660. ret = ar8xxx_start(priv);
  1661. if (ret)
  1662. return ret;
  1663. /* VID fixup only needed on ar8216 */
  1664. if (chip_is_ar8216(priv)) {
  1665. dev->phy_ptr = priv;
  1666. dev->priv_flags |= IFF_NO_IP_ALIGN;
  1667. dev->eth_mangle_rx = ar8216_mangle_rx;
  1668. dev->eth_mangle_tx = ar8216_mangle_tx;
  1669. }
  1670. return 0;
  1671. }
  1672. static bool
  1673. ar8xxx_check_link_states(struct ar8xxx_priv *priv)
  1674. {
  1675. bool link_new, changed = false;
  1676. u32 status;
  1677. int i;
  1678. mutex_lock(&priv->reg_mutex);
  1679. for (i = 0; i < priv->dev.ports; i++) {
  1680. status = priv->chip->read_port_status(priv, i);
  1681. link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
  1682. if (link_new == priv->link_up[i])
  1683. continue;
  1684. priv->link_up[i] = link_new;
  1685. changed = true;
  1686. /* flush ARL entries for this port if it went down*/
  1687. if (!link_new)
  1688. priv->chip->atu_flush_port(priv, i);
  1689. dev_info(&priv->phy->dev, "Port %d is %s\n",
  1690. i, link_new ? "up" : "down");
  1691. }
  1692. mutex_unlock(&priv->reg_mutex);
  1693. return changed;
  1694. }
  1695. static int
  1696. ar8xxx_phy_read_status(struct phy_device *phydev)
  1697. {
  1698. struct ar8xxx_priv *priv = phydev->priv;
  1699. struct switch_port_link link;
  1700. /* check for switch port link changes */
  1701. if (phydev->state == PHY_CHANGELINK)
  1702. ar8xxx_check_link_states(priv);
  1703. if (phydev->addr != 0)
  1704. return genphy_read_status(phydev);
  1705. ar8216_read_port_link(priv, phydev->addr, &link);
  1706. phydev->link = !!link.link;
  1707. if (!phydev->link)
  1708. return 0;
  1709. switch (link.speed) {
  1710. case SWITCH_PORT_SPEED_10:
  1711. phydev->speed = SPEED_10;
  1712. break;
  1713. case SWITCH_PORT_SPEED_100:
  1714. phydev->speed = SPEED_100;
  1715. break;
  1716. case SWITCH_PORT_SPEED_1000:
  1717. phydev->speed = SPEED_1000;
  1718. break;
  1719. default:
  1720. phydev->speed = 0;
  1721. }
  1722. phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
  1723. phydev->state = PHY_RUNNING;
  1724. netif_carrier_on(phydev->attached_dev);
  1725. phydev->adjust_link(phydev->attached_dev);
  1726. return 0;
  1727. }
  1728. static int
  1729. ar8xxx_phy_config_aneg(struct phy_device *phydev)
  1730. {
  1731. if (phydev->addr == 0)
  1732. return 0;
  1733. return genphy_config_aneg(phydev);
  1734. }
  1735. static const u32 ar8xxx_phy_ids[] = {
  1736. 0x004dd033,
  1737. 0x004dd034, /* AR8327 */
  1738. 0x004dd036, /* AR8337 */
  1739. 0x004dd041,
  1740. 0x004dd042,
  1741. 0x004dd043, /* AR8236 */
  1742. };
  1743. static bool
  1744. ar8xxx_phy_match(u32 phy_id)
  1745. {
  1746. int i;
  1747. for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
  1748. if (phy_id == ar8xxx_phy_ids[i])
  1749. return true;
  1750. return false;
  1751. }
  1752. static bool
  1753. ar8xxx_is_possible(struct mii_bus *bus)
  1754. {
  1755. unsigned int i, found_phys = 0;
  1756. for (i = 0; i < 5; i++) {
  1757. u32 phy_id;
  1758. phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
  1759. phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
  1760. if (ar8xxx_phy_match(phy_id)) {
  1761. found_phys++;
  1762. } else if (phy_id) {
  1763. pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
  1764. dev_name(&bus->dev), i, phy_id);
  1765. }
  1766. }
  1767. return !!found_phys;
  1768. }
  1769. static int
  1770. ar8xxx_phy_probe(struct phy_device *phydev)
  1771. {
  1772. struct ar8xxx_priv *priv;
  1773. struct switch_dev *swdev;
  1774. int ret;
  1775. /* skip PHYs at unused adresses */
  1776. if (phydev->addr != 0 && phydev->addr != 4)
  1777. return -ENODEV;
  1778. if (!ar8xxx_is_possible(phydev->bus))
  1779. return -ENODEV;
  1780. mutex_lock(&ar8xxx_dev_list_lock);
  1781. list_for_each_entry(priv, &ar8xxx_dev_list, list)
  1782. if (priv->mii_bus == phydev->bus)
  1783. goto found;
  1784. priv = ar8xxx_create();
  1785. if (priv == NULL) {
  1786. ret = -ENOMEM;
  1787. goto unlock;
  1788. }
  1789. priv->mii_bus = phydev->bus;
  1790. ret = ar8xxx_probe_switch(priv);
  1791. if (ret)
  1792. goto free_priv;
  1793. swdev = &priv->dev;
  1794. swdev->alias = dev_name(&priv->mii_bus->dev);
  1795. ret = register_switch(swdev, NULL);
  1796. if (ret)
  1797. goto free_priv;
  1798. pr_info("%s: %s rev. %u switch registered on %s\n",
  1799. swdev->devname, swdev->name, priv->chip_rev,
  1800. dev_name(&priv->mii_bus->dev));
  1801. list_add(&priv->list, &ar8xxx_dev_list);
  1802. found:
  1803. priv->use_count++;
  1804. if (phydev->addr == 0) {
  1805. if (ar8xxx_has_gige(priv)) {
  1806. phydev->supported = SUPPORTED_1000baseT_Full;
  1807. phydev->advertising = ADVERTISED_1000baseT_Full;
  1808. } else {
  1809. phydev->supported = SUPPORTED_100baseT_Full;
  1810. phydev->advertising = ADVERTISED_100baseT_Full;
  1811. }
  1812. if (priv->chip->config_at_probe) {
  1813. priv->phy = phydev;
  1814. ret = ar8xxx_start(priv);
  1815. if (ret)
  1816. goto err_unregister_switch;
  1817. }
  1818. } else {
  1819. if (ar8xxx_has_gige(priv)) {
  1820. phydev->supported |= SUPPORTED_1000baseT_Full;
  1821. phydev->advertising |= ADVERTISED_1000baseT_Full;
  1822. }
  1823. }
  1824. phydev->priv = priv;
  1825. mutex_unlock(&ar8xxx_dev_list_lock);
  1826. return 0;
  1827. err_unregister_switch:
  1828. if (--priv->use_count)
  1829. goto unlock;
  1830. unregister_switch(&priv->dev);
  1831. free_priv:
  1832. ar8xxx_free(priv);
  1833. unlock:
  1834. mutex_unlock(&ar8xxx_dev_list_lock);
  1835. return ret;
  1836. }
  1837. static void
  1838. ar8xxx_phy_detach(struct phy_device *phydev)
  1839. {
  1840. struct net_device *dev = phydev->attached_dev;
  1841. if (!dev)
  1842. return;
  1843. dev->phy_ptr = NULL;
  1844. dev->priv_flags &= ~IFF_NO_IP_ALIGN;
  1845. dev->eth_mangle_rx = NULL;
  1846. dev->eth_mangle_tx = NULL;
  1847. }
  1848. static void
  1849. ar8xxx_phy_remove(struct phy_device *phydev)
  1850. {
  1851. struct ar8xxx_priv *priv = phydev->priv;
  1852. if (WARN_ON(!priv))
  1853. return;
  1854. phydev->priv = NULL;
  1855. mutex_lock(&ar8xxx_dev_list_lock);
  1856. if (--priv->use_count > 0) {
  1857. mutex_unlock(&ar8xxx_dev_list_lock);
  1858. return;
  1859. }
  1860. list_del(&priv->list);
  1861. mutex_unlock(&ar8xxx_dev_list_lock);
  1862. unregister_switch(&priv->dev);
  1863. ar8xxx_mib_stop(priv);
  1864. ar8xxx_free(priv);
  1865. }
  1866. #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
  1867. static int
  1868. ar8xxx_phy_soft_reset(struct phy_device *phydev)
  1869. {
  1870. /* we don't need an extra reset */
  1871. return 0;
  1872. }
  1873. #endif
  1874. static struct phy_driver ar8xxx_phy_driver = {
  1875. .phy_id = 0x004d0000,
  1876. .name = "Atheros AR8216/AR8236/AR8316",
  1877. .phy_id_mask = 0xffff0000,
  1878. .features = PHY_BASIC_FEATURES,
  1879. .probe = ar8xxx_phy_probe,
  1880. .remove = ar8xxx_phy_remove,
  1881. .detach = ar8xxx_phy_detach,
  1882. .config_init = ar8xxx_phy_config_init,
  1883. .config_aneg = ar8xxx_phy_config_aneg,
  1884. .read_status = ar8xxx_phy_read_status,
  1885. #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
  1886. .soft_reset = ar8xxx_phy_soft_reset,
  1887. #endif
  1888. .driver = { .owner = THIS_MODULE },
  1889. };
  1890. int __init
  1891. ar8xxx_init(void)
  1892. {
  1893. return phy_driver_register(&ar8xxx_phy_driver);
  1894. }
  1895. void __exit
  1896. ar8xxx_exit(void)
  1897. {
  1898. phy_driver_unregister(&ar8xxx_phy_driver);
  1899. }
  1900. module_init(ar8xxx_init);
  1901. module_exit(ar8xxx_exit);
  1902. MODULE_LICENSE("GPL");