rtl8366s.c 29 KB

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  1. /*
  2. * Platform driver for the Realtek RTL8366S ethernet switch
  3. *
  4. * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
  5. * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published
  9. * by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/device.h>
  15. #include <linux/of.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/delay.h>
  18. #include <linux/skbuff.h>
  19. #include <linux/rtl8366.h>
  20. #include "rtl8366_smi.h"
  21. #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
  22. #define RTL8366S_DRIVER_VER "0.2.2"
  23. #define RTL8366S_PHY_NO_MAX 4
  24. #define RTL8366S_PHY_PAGE_MAX 7
  25. #define RTL8366S_PHY_ADDR_MAX 31
  26. /* Switch Global Configuration register */
  27. #define RTL8366S_SGCR 0x0000
  28. #define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0)
  29. #define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4)
  30. #define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3)
  31. #define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0)
  32. #define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1)
  33. #define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2)
  34. #define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3)
  35. #define RTL8366S_SGCR_EN_VLAN BIT(13)
  36. /* Port Enable Control register */
  37. #define RTL8366S_PECR 0x0001
  38. /* Switch Security Control registers */
  39. #define RTL8366S_SSCR0 0x0002
  40. #define RTL8366S_SSCR1 0x0003
  41. #define RTL8366S_SSCR2 0x0004
  42. #define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0)
  43. #define RTL8366S_RESET_CTRL_REG 0x0100
  44. #define RTL8366S_CHIP_CTRL_RESET_HW 1
  45. #define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1)
  46. #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
  47. #define RTL8366S_CHIP_VERSION_MASK 0xf
  48. #define RTL8366S_CHIP_ID_REG 0x0105
  49. #define RTL8366S_CHIP_ID_8366 0x8366
  50. /* PHY registers control */
  51. #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
  52. #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
  53. #define RTL8366S_PHY_CTRL_READ 1
  54. #define RTL8366S_PHY_CTRL_WRITE 0
  55. #define RTL8366S_PHY_REG_MASK 0x1f
  56. #define RTL8366S_PHY_PAGE_OFFSET 5
  57. #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
  58. #define RTL8366S_PHY_NO_OFFSET 9
  59. #define RTL8366S_PHY_NO_MASK (0x1f << 9)
  60. /* LED control registers */
  61. #define RTL8366S_LED_BLINKRATE_REG 0x0420
  62. #define RTL8366S_LED_BLINKRATE_BIT 0
  63. #define RTL8366S_LED_BLINKRATE_MASK 0x0007
  64. #define RTL8366S_LED_CTRL_REG 0x0421
  65. #define RTL8366S_LED_0_1_CTRL_REG 0x0422
  66. #define RTL8366S_LED_2_3_CTRL_REG 0x0423
  67. #define RTL8366S_MIB_COUNT 33
  68. #define RTL8366S_GLOBAL_MIB_COUNT 1
  69. #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
  70. #define RTL8366S_MIB_COUNTER_BASE 0x1000
  71. #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
  72. #define RTL8366S_MIB_COUNTER_BASE2 0x1180
  73. #define RTL8366S_MIB_CTRL_REG 0x11F0
  74. #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
  75. #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
  76. #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
  77. #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
  78. #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
  79. #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
  80. #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
  81. #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
  82. (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
  83. #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
  84. #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
  85. #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
  86. #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
  87. #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
  88. #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
  89. #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
  90. #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
  91. #define RTL8366S_VLAN_MC_BASE(_x) (0x0016 + (_x) * 2)
  92. #define RTL8366S_VLAN_MEMBERINGRESS_REG 0x0379
  93. #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
  94. #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
  95. #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
  96. #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
  97. #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
  98. #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
  99. #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
  100. #define RTL8366S_PORT_NUM_CPU 5
  101. #define RTL8366S_NUM_PORTS 6
  102. #define RTL8366S_NUM_VLANS 16
  103. #define RTL8366S_NUM_LEDGROUPS 4
  104. #define RTL8366S_NUM_VIDS 4096
  105. #define RTL8366S_PRIORITYMAX 7
  106. #define RTL8366S_FIDMAX 7
  107. #define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */
  108. #define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */
  109. #define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */
  110. #define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */
  111. #define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */
  112. #define RTL8366S_PORT_CPU (1 << 5) /* CPU port */
  113. #define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \
  114. RTL8366S_PORT_2 | \
  115. RTL8366S_PORT_3 | \
  116. RTL8366S_PORT_4 | \
  117. RTL8366S_PORT_UNKNOWN | \
  118. RTL8366S_PORT_CPU)
  119. #define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \
  120. RTL8366S_PORT_2 | \
  121. RTL8366S_PORT_3 | \
  122. RTL8366S_PORT_4 | \
  123. RTL8366S_PORT_UNKNOWN)
  124. #define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \
  125. RTL8366S_PORT_2 | \
  126. RTL8366S_PORT_3 | \
  127. RTL8366S_PORT_4)
  128. #define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \
  129. RTL8366S_PORT_CPU)
  130. #define RTL8366S_VLAN_VID_MASK 0xfff
  131. #define RTL8366S_VLAN_PRIORITY_SHIFT 12
  132. #define RTL8366S_VLAN_PRIORITY_MASK 0x7
  133. #define RTL8366S_VLAN_MEMBER_MASK 0x3f
  134. #define RTL8366S_VLAN_UNTAG_SHIFT 6
  135. #define RTL8366S_VLAN_UNTAG_MASK 0x3f
  136. #define RTL8366S_VLAN_FID_SHIFT 12
  137. #define RTL8366S_VLAN_FID_MASK 0x7
  138. static struct rtl8366_mib_counter rtl8366s_mib_counters[] = {
  139. { 0, 0, 4, "IfInOctets" },
  140. { 0, 4, 4, "EtherStatsOctets" },
  141. { 0, 8, 2, "EtherStatsUnderSizePkts" },
  142. { 0, 10, 2, "EtherFragments" },
  143. { 0, 12, 2, "EtherStatsPkts64Octets" },
  144. { 0, 14, 2, "EtherStatsPkts65to127Octets" },
  145. { 0, 16, 2, "EtherStatsPkts128to255Octets" },
  146. { 0, 18, 2, "EtherStatsPkts256to511Octets" },
  147. { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
  148. { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
  149. { 0, 24, 2, "EtherOversizeStats" },
  150. { 0, 26, 2, "EtherStatsJabbers" },
  151. { 0, 28, 2, "IfInUcastPkts" },
  152. { 0, 30, 2, "EtherStatsMulticastPkts" },
  153. { 0, 32, 2, "EtherStatsBroadcastPkts" },
  154. { 0, 34, 2, "EtherStatsDropEvents" },
  155. { 0, 36, 2, "Dot3StatsFCSErrors" },
  156. { 0, 38, 2, "Dot3StatsSymbolErrors" },
  157. { 0, 40, 2, "Dot3InPauseFrames" },
  158. { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
  159. { 0, 44, 4, "IfOutOctets" },
  160. { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
  161. { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
  162. { 0, 52, 2, "Dot3sDeferredTransmissions" },
  163. { 0, 54, 2, "Dot3StatsLateCollisions" },
  164. { 0, 56, 2, "EtherStatsCollisions" },
  165. { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
  166. { 0, 60, 2, "Dot3OutPauseFrames" },
  167. { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
  168. /*
  169. * The following counters are accessible at a different
  170. * base address.
  171. */
  172. { 1, 0, 2, "Dot1dTpPortInDiscards" },
  173. { 1, 2, 2, "IfOutUcastPkts" },
  174. { 1, 4, 2, "IfOutMulticastPkts" },
  175. { 1, 6, 2, "IfOutBroadcastPkts" },
  176. };
  177. #define REG_WR(_smi, _reg, _val) \
  178. do { \
  179. err = rtl8366_smi_write_reg(_smi, _reg, _val); \
  180. if (err) \
  181. return err; \
  182. } while (0)
  183. #define REG_RMW(_smi, _reg, _mask, _val) \
  184. do { \
  185. err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
  186. if (err) \
  187. return err; \
  188. } while (0)
  189. static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
  190. {
  191. int timeout = 10;
  192. u32 data;
  193. rtl8366_smi_write_reg_noack(smi, RTL8366S_RESET_CTRL_REG,
  194. RTL8366S_CHIP_CTRL_RESET_HW);
  195. do {
  196. msleep(1);
  197. if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
  198. return -EIO;
  199. if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
  200. break;
  201. } while (--timeout);
  202. if (!timeout) {
  203. printk("Timeout waiting for the switch to reset\n");
  204. return -EIO;
  205. }
  206. return 0;
  207. }
  208. static int rtl8366s_setup(struct rtl8366_smi *smi)
  209. {
  210. struct rtl8366_platform_data *pdata;
  211. int err;
  212. pdata = smi->parent->platform_data;
  213. if (pdata && pdata->num_initvals && pdata->initvals) {
  214. unsigned i;
  215. dev_info(smi->parent, "applying initvals\n");
  216. for (i = 0; i < pdata->num_initvals; i++)
  217. REG_WR(smi, pdata->initvals[i].reg,
  218. pdata->initvals[i].val);
  219. }
  220. /* set maximum packet length to 1536 bytes */
  221. REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
  222. RTL8366S_SGCR_MAX_LENGTH_1536);
  223. /* enable learning for all ports */
  224. REG_WR(smi, RTL8366S_SSCR0, 0);
  225. /* enable auto ageing for all ports */
  226. REG_WR(smi, RTL8366S_SSCR1, 0);
  227. /*
  228. * discard VLAN tagged packets if the port is not a member of
  229. * the VLAN with which the packets is associated.
  230. */
  231. REG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);
  232. /* don't drop packets whose DA has not been learned */
  233. REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
  234. return 0;
  235. }
  236. static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
  237. u32 phy_no, u32 page, u32 addr, u32 *data)
  238. {
  239. u32 reg;
  240. int ret;
  241. if (phy_no > RTL8366S_PHY_NO_MAX)
  242. return -EINVAL;
  243. if (page > RTL8366S_PHY_PAGE_MAX)
  244. return -EINVAL;
  245. if (addr > RTL8366S_PHY_ADDR_MAX)
  246. return -EINVAL;
  247. ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
  248. RTL8366S_PHY_CTRL_READ);
  249. if (ret)
  250. return ret;
  251. reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
  252. ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
  253. (addr & RTL8366S_PHY_REG_MASK);
  254. ret = rtl8366_smi_write_reg(smi, reg, 0);
  255. if (ret)
  256. return ret;
  257. ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
  258. if (ret)
  259. return ret;
  260. return 0;
  261. }
  262. static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
  263. u32 phy_no, u32 page, u32 addr, u32 data)
  264. {
  265. u32 reg;
  266. int ret;
  267. if (phy_no > RTL8366S_PHY_NO_MAX)
  268. return -EINVAL;
  269. if (page > RTL8366S_PHY_PAGE_MAX)
  270. return -EINVAL;
  271. if (addr > RTL8366S_PHY_ADDR_MAX)
  272. return -EINVAL;
  273. ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
  274. RTL8366S_PHY_CTRL_WRITE);
  275. if (ret)
  276. return ret;
  277. reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
  278. ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
  279. (addr & RTL8366S_PHY_REG_MASK);
  280. ret = rtl8366_smi_write_reg(smi, reg, data);
  281. if (ret)
  282. return ret;
  283. return 0;
  284. }
  285. static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
  286. int port, unsigned long long *val)
  287. {
  288. int i;
  289. int err;
  290. u32 addr, data;
  291. u64 mibvalue;
  292. if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
  293. return -EINVAL;
  294. switch (rtl8366s_mib_counters[counter].base) {
  295. case 0:
  296. addr = RTL8366S_MIB_COUNTER_BASE +
  297. RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
  298. break;
  299. case 1:
  300. addr = RTL8366S_MIB_COUNTER_BASE2 +
  301. RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
  302. break;
  303. default:
  304. return -EINVAL;
  305. }
  306. addr += rtl8366s_mib_counters[counter].offset;
  307. /*
  308. * Writing access counter address first
  309. * then ASIC will prepare 64bits counter wait for being retrived
  310. */
  311. data = 0; /* writing data will be discard by ASIC */
  312. err = rtl8366_smi_write_reg(smi, addr, data);
  313. if (err)
  314. return err;
  315. /* read MIB control register */
  316. err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
  317. if (err)
  318. return err;
  319. if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
  320. return -EBUSY;
  321. if (data & RTL8366S_MIB_CTRL_RESET_MASK)
  322. return -EIO;
  323. mibvalue = 0;
  324. for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
  325. err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
  326. if (err)
  327. return err;
  328. mibvalue = (mibvalue << 16) | (data & 0xFFFF);
  329. }
  330. *val = mibvalue;
  331. return 0;
  332. }
  333. static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
  334. struct rtl8366_vlan_4k *vlan4k)
  335. {
  336. u32 data[2];
  337. int err;
  338. int i;
  339. memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
  340. if (vid >= RTL8366S_NUM_VIDS)
  341. return -EINVAL;
  342. /* write VID */
  343. err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE,
  344. vid & RTL8366S_VLAN_VID_MASK);
  345. if (err)
  346. return err;
  347. /* write table access control word */
  348. err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
  349. RTL8366S_TABLE_VLAN_READ_CTRL);
  350. if (err)
  351. return err;
  352. for (i = 0; i < 2; i++) {
  353. err = rtl8366_smi_read_reg(smi,
  354. RTL8366S_VLAN_TABLE_READ_BASE + i,
  355. &data[i]);
  356. if (err)
  357. return err;
  358. }
  359. vlan4k->vid = vid;
  360. vlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
  361. RTL8366S_VLAN_UNTAG_MASK;
  362. vlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
  363. vlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
  364. RTL8366S_VLAN_FID_MASK;
  365. return 0;
  366. }
  367. static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
  368. const struct rtl8366_vlan_4k *vlan4k)
  369. {
  370. u32 data[2];
  371. int err;
  372. int i;
  373. if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
  374. vlan4k->member > RTL8366S_VLAN_MEMBER_MASK ||
  375. vlan4k->untag > RTL8366S_VLAN_UNTAG_MASK ||
  376. vlan4k->fid > RTL8366S_FIDMAX)
  377. return -EINVAL;
  378. data[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK;
  379. data[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) |
  380. ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) <<
  381. RTL8366S_VLAN_UNTAG_SHIFT) |
  382. ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) <<
  383. RTL8366S_VLAN_FID_SHIFT);
  384. for (i = 0; i < 2; i++) {
  385. err = rtl8366_smi_write_reg(smi,
  386. RTL8366S_VLAN_TABLE_WRITE_BASE + i,
  387. data[i]);
  388. if (err)
  389. return err;
  390. }
  391. /* write table access control word */
  392. err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
  393. RTL8366S_TABLE_VLAN_WRITE_CTRL);
  394. return err;
  395. }
  396. static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
  397. struct rtl8366_vlan_mc *vlanmc)
  398. {
  399. u32 data[2];
  400. int err;
  401. int i;
  402. memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
  403. if (index >= RTL8366S_NUM_VLANS)
  404. return -EINVAL;
  405. for (i = 0; i < 2; i++) {
  406. err = rtl8366_smi_read_reg(smi,
  407. RTL8366S_VLAN_MC_BASE(index) + i,
  408. &data[i]);
  409. if (err)
  410. return err;
  411. }
  412. vlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK;
  413. vlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) &
  414. RTL8366S_VLAN_PRIORITY_MASK;
  415. vlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &
  416. RTL8366S_VLAN_UNTAG_MASK;
  417. vlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;
  418. vlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &
  419. RTL8366S_VLAN_FID_MASK;
  420. return 0;
  421. }
  422. static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
  423. const struct rtl8366_vlan_mc *vlanmc)
  424. {
  425. u32 data[2];
  426. int err;
  427. int i;
  428. if (index >= RTL8366S_NUM_VLANS ||
  429. vlanmc->vid >= RTL8366S_NUM_VIDS ||
  430. vlanmc->priority > RTL8366S_PRIORITYMAX ||
  431. vlanmc->member > RTL8366S_VLAN_MEMBER_MASK ||
  432. vlanmc->untag > RTL8366S_VLAN_UNTAG_MASK ||
  433. vlanmc->fid > RTL8366S_FIDMAX)
  434. return -EINVAL;
  435. data[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) |
  436. ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) <<
  437. RTL8366S_VLAN_PRIORITY_SHIFT);
  438. data[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) |
  439. ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) <<
  440. RTL8366S_VLAN_UNTAG_SHIFT) |
  441. ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) <<
  442. RTL8366S_VLAN_FID_SHIFT);
  443. for (i = 0; i < 2; i++) {
  444. err = rtl8366_smi_write_reg(smi,
  445. RTL8366S_VLAN_MC_BASE(index) + i,
  446. data[i]);
  447. if (err)
  448. return err;
  449. }
  450. return 0;
  451. }
  452. static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
  453. {
  454. u32 data;
  455. int err;
  456. if (port >= RTL8366S_NUM_PORTS)
  457. return -EINVAL;
  458. err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
  459. &data);
  460. if (err)
  461. return err;
  462. *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
  463. RTL8366S_PORT_VLAN_CTRL_MASK;
  464. return 0;
  465. }
  466. static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
  467. {
  468. if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
  469. return -EINVAL;
  470. return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
  471. RTL8366S_PORT_VLAN_CTRL_MASK <<
  472. RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
  473. (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
  474. RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
  475. }
  476. static int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable)
  477. {
  478. return rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,
  479. (enable) ? RTL8366S_SGCR_EN_VLAN : 0);
  480. }
  481. static int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable)
  482. {
  483. return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
  484. 1, (enable) ? 1 : 0);
  485. }
  486. static int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)
  487. {
  488. unsigned max = RTL8366S_NUM_VLANS;
  489. if (smi->vlan4k_enabled)
  490. max = RTL8366S_NUM_VIDS - 1;
  491. if (vlan == 0 || vlan >= max)
  492. return 0;
  493. return 1;
  494. }
  495. static int rtl8366s_enable_port(struct rtl8366_smi *smi, int port, int enable)
  496. {
  497. return rtl8366_smi_rmwr(smi, RTL8366S_PECR, (1 << port),
  498. (enable) ? 0 : (1 << port));
  499. }
  500. static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
  501. const struct switch_attr *attr,
  502. struct switch_val *val)
  503. {
  504. struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
  505. return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
  506. }
  507. static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
  508. const struct switch_attr *attr,
  509. struct switch_val *val)
  510. {
  511. struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
  512. u32 data;
  513. rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
  514. val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
  515. return 0;
  516. }
  517. static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
  518. const struct switch_attr *attr,
  519. struct switch_val *val)
  520. {
  521. struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
  522. if (val->value.i >= 6)
  523. return -EINVAL;
  524. return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
  525. RTL8366S_LED_BLINKRATE_MASK,
  526. val->value.i);
  527. }
  528. static int rtl8366s_sw_get_max_length(struct switch_dev *dev,
  529. const struct switch_attr *attr,
  530. struct switch_val *val)
  531. {
  532. struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
  533. u32 data;
  534. rtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data);
  535. val->value.i = ((data & (RTL8366S_SGCR_MAX_LENGTH_MASK)) >> 4);
  536. return 0;
  537. }
  538. static int rtl8366s_sw_set_max_length(struct switch_dev *dev,
  539. const struct switch_attr *attr,
  540. struct switch_val *val)
  541. {
  542. struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
  543. char length_code;
  544. switch (val->value.i) {
  545. case 0:
  546. length_code = RTL8366S_SGCR_MAX_LENGTH_1522;
  547. break;
  548. case 1:
  549. length_code = RTL8366S_SGCR_MAX_LENGTH_1536;
  550. break;
  551. case 2:
  552. length_code = RTL8366S_SGCR_MAX_LENGTH_1552;
  553. break;
  554. case 3:
  555. length_code = RTL8366S_SGCR_MAX_LENGTH_16000;
  556. break;
  557. default:
  558. return -EINVAL;
  559. }
  560. return rtl8366_smi_rmwr(smi, RTL8366S_SGCR,
  561. RTL8366S_SGCR_MAX_LENGTH_MASK,
  562. length_code);
  563. }
  564. static int rtl8366s_sw_get_learning_enable(struct switch_dev *dev,
  565. const struct switch_attr *attr,
  566. struct switch_val *val)
  567. {
  568. struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
  569. u32 data;
  570. rtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data);
  571. val->value.i = !data;
  572. return 0;
  573. }
  574. static int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,
  575. const struct switch_attr *attr,
  576. struct switch_val *val)
  577. {
  578. struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
  579. u32 portmask = 0;
  580. int err = 0;
  581. if (!val->value.i)
  582. portmask = RTL8366S_PORT_ALL;
  583. /* set learning for all ports */
  584. REG_WR(smi, RTL8366S_SSCR0, portmask);
  585. /* set auto ageing for all ports */
  586. REG_WR(smi, RTL8366S_SSCR1, portmask);
  587. return 0;
  588. }
  589. static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
  590. int port,
  591. struct switch_port_link *link)
  592. {
  593. struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
  594. u32 data = 0;
  595. u32 speed;
  596. if (port >= RTL8366S_NUM_PORTS)
  597. return -EINVAL;
  598. rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE + (port / 2),
  599. &data);
  600. if (port % 2)
  601. data = data >> 8;
  602. link->link = !!(data & RTL8366S_PORT_STATUS_LINK_MASK);
  603. if (!link->link)
  604. return 0;
  605. link->duplex = !!(data & RTL8366S_PORT_STATUS_DUPLEX_MASK);
  606. link->rx_flow = !!(data & RTL8366S_PORT_STATUS_RXPAUSE_MASK);
  607. link->tx_flow = !!(data & RTL8366S_PORT_STATUS_TXPAUSE_MASK);
  608. link->aneg = !!(data & RTL8366S_PORT_STATUS_AN_MASK);
  609. speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
  610. switch (speed) {
  611. case 0:
  612. link->speed = SWITCH_PORT_SPEED_10;
  613. break;
  614. case 1:
  615. link->speed = SWITCH_PORT_SPEED_100;
  616. break;
  617. case 2:
  618. link->speed = SWITCH_PORT_SPEED_1000;
  619. break;
  620. default:
  621. link->speed = SWITCH_PORT_SPEED_UNKNOWN;
  622. break;
  623. }
  624. return 0;
  625. }
  626. static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
  627. const struct switch_attr *attr,
  628. struct switch_val *val)
  629. {
  630. struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
  631. u32 data;
  632. u32 mask;
  633. u32 reg;
  634. if (val->port_vlan >= RTL8366S_NUM_PORTS ||
  635. (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
  636. return -EINVAL;
  637. if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
  638. reg = RTL8366S_LED_BLINKRATE_REG;
  639. mask = 0xF << 4;
  640. data = val->value.i << 4;
  641. } else {
  642. reg = RTL8366S_LED_CTRL_REG;
  643. mask = 0xF << (val->port_vlan * 4),
  644. data = val->value.i << (val->port_vlan * 4);
  645. }
  646. return rtl8366_smi_rmwr(smi, reg, mask, data);
  647. }
  648. static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
  649. const struct switch_attr *attr,
  650. struct switch_val *val)
  651. {
  652. struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
  653. u32 data = 0;
  654. if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
  655. return -EINVAL;
  656. rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
  657. val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
  658. return 0;
  659. }
  660. static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
  661. const struct switch_attr *attr,
  662. struct switch_val *val)
  663. {
  664. struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
  665. if (val->port_vlan >= RTL8366S_NUM_PORTS)
  666. return -EINVAL;
  667. return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
  668. 0, (1 << (val->port_vlan + 3)));
  669. }
  670. static struct switch_attr rtl8366s_globals[] = {
  671. {
  672. .type = SWITCH_TYPE_INT,
  673. .name = "enable_learning",
  674. .description = "Enable learning, enable aging",
  675. .set = rtl8366s_sw_set_learning_enable,
  676. .get = rtl8366s_sw_get_learning_enable,
  677. .max = 1,
  678. }, {
  679. .type = SWITCH_TYPE_INT,
  680. .name = "enable_vlan",
  681. .description = "Enable VLAN mode",
  682. .set = rtl8366_sw_set_vlan_enable,
  683. .get = rtl8366_sw_get_vlan_enable,
  684. .max = 1,
  685. .ofs = 1
  686. }, {
  687. .type = SWITCH_TYPE_INT,
  688. .name = "enable_vlan4k",
  689. .description = "Enable VLAN 4K mode",
  690. .set = rtl8366_sw_set_vlan_enable,
  691. .get = rtl8366_sw_get_vlan_enable,
  692. .max = 1,
  693. .ofs = 2
  694. }, {
  695. .type = SWITCH_TYPE_NOVAL,
  696. .name = "reset_mibs",
  697. .description = "Reset all MIB counters",
  698. .set = rtl8366s_sw_reset_mibs,
  699. }, {
  700. .type = SWITCH_TYPE_INT,
  701. .name = "blinkrate",
  702. .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
  703. " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
  704. .set = rtl8366s_sw_set_blinkrate,
  705. .get = rtl8366s_sw_get_blinkrate,
  706. .max = 5
  707. }, {
  708. .type = SWITCH_TYPE_INT,
  709. .name = "max_length",
  710. .description = "Get/Set the maximum length of valid packets"
  711. " (0 = 1522, 1 = 1536, 2 = 1552, 3 = 16000 (9216?))",
  712. .set = rtl8366s_sw_set_max_length,
  713. .get = rtl8366s_sw_get_max_length,
  714. .max = 3,
  715. },
  716. };
  717. static struct switch_attr rtl8366s_port[] = {
  718. {
  719. .type = SWITCH_TYPE_NOVAL,
  720. .name = "reset_mib",
  721. .description = "Reset single port MIB counters",
  722. .set = rtl8366s_sw_reset_port_mibs,
  723. }, {
  724. .type = SWITCH_TYPE_STRING,
  725. .name = "mib",
  726. .description = "Get MIB counters for port",
  727. .max = 33,
  728. .set = NULL,
  729. .get = rtl8366_sw_get_port_mib,
  730. }, {
  731. .type = SWITCH_TYPE_INT,
  732. .name = "led",
  733. .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
  734. .max = 15,
  735. .set = rtl8366s_sw_set_port_led,
  736. .get = rtl8366s_sw_get_port_led,
  737. },
  738. };
  739. static struct switch_attr rtl8366s_vlan[] = {
  740. {
  741. .type = SWITCH_TYPE_STRING,
  742. .name = "info",
  743. .description = "Get vlan information",
  744. .max = 1,
  745. .set = NULL,
  746. .get = rtl8366_sw_get_vlan_info,
  747. }, {
  748. .type = SWITCH_TYPE_INT,
  749. .name = "fid",
  750. .description = "Get/Set vlan FID",
  751. .max = RTL8366S_FIDMAX,
  752. .set = rtl8366_sw_set_vlan_fid,
  753. .get = rtl8366_sw_get_vlan_fid,
  754. },
  755. };
  756. static const struct switch_dev_ops rtl8366_ops = {
  757. .attr_global = {
  758. .attr = rtl8366s_globals,
  759. .n_attr = ARRAY_SIZE(rtl8366s_globals),
  760. },
  761. .attr_port = {
  762. .attr = rtl8366s_port,
  763. .n_attr = ARRAY_SIZE(rtl8366s_port),
  764. },
  765. .attr_vlan = {
  766. .attr = rtl8366s_vlan,
  767. .n_attr = ARRAY_SIZE(rtl8366s_vlan),
  768. },
  769. .get_vlan_ports = rtl8366_sw_get_vlan_ports,
  770. .set_vlan_ports = rtl8366_sw_set_vlan_ports,
  771. .get_port_pvid = rtl8366_sw_get_port_pvid,
  772. .set_port_pvid = rtl8366_sw_set_port_pvid,
  773. .reset_switch = rtl8366_sw_reset_switch,
  774. .get_port_link = rtl8366s_sw_get_port_link,
  775. };
  776. static int rtl8366s_switch_init(struct rtl8366_smi *smi)
  777. {
  778. struct switch_dev *dev = &smi->sw_dev;
  779. int err;
  780. dev->name = "RTL8366S";
  781. dev->cpu_port = RTL8366S_PORT_NUM_CPU;
  782. dev->ports = RTL8366S_NUM_PORTS;
  783. dev->vlans = RTL8366S_NUM_VIDS;
  784. dev->ops = &rtl8366_ops;
  785. dev->alias = dev_name(smi->parent);
  786. err = register_switch(dev, NULL);
  787. if (err)
  788. dev_err(smi->parent, "switch registration failed\n");
  789. return err;
  790. }
  791. static void rtl8366s_switch_cleanup(struct rtl8366_smi *smi)
  792. {
  793. unregister_switch(&smi->sw_dev);
  794. }
  795. static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
  796. {
  797. struct rtl8366_smi *smi = bus->priv;
  798. u32 val = 0;
  799. int err;
  800. err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
  801. if (err)
  802. return 0xffff;
  803. return val;
  804. }
  805. static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
  806. {
  807. struct rtl8366_smi *smi = bus->priv;
  808. u32 t;
  809. int err;
  810. err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
  811. /* flush write */
  812. (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
  813. return err;
  814. }
  815. static int rtl8366s_detect(struct rtl8366_smi *smi)
  816. {
  817. u32 chip_id = 0;
  818. u32 chip_ver = 0;
  819. int ret;
  820. ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
  821. if (ret) {
  822. dev_err(smi->parent, "unable to read chip id\n");
  823. return ret;
  824. }
  825. switch (chip_id) {
  826. case RTL8366S_CHIP_ID_8366:
  827. break;
  828. default:
  829. dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
  830. return -ENODEV;
  831. }
  832. ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
  833. &chip_ver);
  834. if (ret) {
  835. dev_err(smi->parent, "unable to read chip version\n");
  836. return ret;
  837. }
  838. dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
  839. chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
  840. return 0;
  841. }
  842. static struct rtl8366_smi_ops rtl8366s_smi_ops = {
  843. .detect = rtl8366s_detect,
  844. .reset_chip = rtl8366s_reset_chip,
  845. .setup = rtl8366s_setup,
  846. .mii_read = rtl8366s_mii_read,
  847. .mii_write = rtl8366s_mii_write,
  848. .get_vlan_mc = rtl8366s_get_vlan_mc,
  849. .set_vlan_mc = rtl8366s_set_vlan_mc,
  850. .get_vlan_4k = rtl8366s_get_vlan_4k,
  851. .set_vlan_4k = rtl8366s_set_vlan_4k,
  852. .get_mc_index = rtl8366s_get_mc_index,
  853. .set_mc_index = rtl8366s_set_mc_index,
  854. .get_mib_counter = rtl8366_get_mib_counter,
  855. .is_vlan_valid = rtl8366s_is_vlan_valid,
  856. .enable_vlan = rtl8366s_enable_vlan,
  857. .enable_vlan4k = rtl8366s_enable_vlan4k,
  858. .enable_port = rtl8366s_enable_port,
  859. };
  860. static int rtl8366s_probe(struct platform_device *pdev)
  861. {
  862. static int rtl8366_smi_version_printed;
  863. struct rtl8366_smi *smi;
  864. int err;
  865. if (!rtl8366_smi_version_printed++)
  866. printk(KERN_NOTICE RTL8366S_DRIVER_DESC
  867. " version " RTL8366S_DRIVER_VER"\n");
  868. smi = rtl8366_smi_probe(pdev);
  869. if (!smi)
  870. return -ENODEV;
  871. smi->clk_delay = 10;
  872. smi->cmd_read = 0xa9;
  873. smi->cmd_write = 0xa8;
  874. smi->ops = &rtl8366s_smi_ops;
  875. smi->cpu_port = RTL8366S_PORT_NUM_CPU;
  876. smi->num_ports = RTL8366S_NUM_PORTS;
  877. smi->num_vlan_mc = RTL8366S_NUM_VLANS;
  878. smi->mib_counters = rtl8366s_mib_counters;
  879. smi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);
  880. err = rtl8366_smi_init(smi);
  881. if (err)
  882. goto err_free_smi;
  883. platform_set_drvdata(pdev, smi);
  884. err = rtl8366s_switch_init(smi);
  885. if (err)
  886. goto err_clear_drvdata;
  887. return 0;
  888. err_clear_drvdata:
  889. platform_set_drvdata(pdev, NULL);
  890. rtl8366_smi_cleanup(smi);
  891. err_free_smi:
  892. kfree(smi);
  893. return err;
  894. }
  895. static int rtl8366s_remove(struct platform_device *pdev)
  896. {
  897. struct rtl8366_smi *smi = platform_get_drvdata(pdev);
  898. if (smi) {
  899. rtl8366s_switch_cleanup(smi);
  900. platform_set_drvdata(pdev, NULL);
  901. rtl8366_smi_cleanup(smi);
  902. kfree(smi);
  903. }
  904. return 0;
  905. }
  906. #ifdef CONFIG_OF
  907. static const struct of_device_id rtl8366s_match[] = {
  908. { .compatible = "realtek,rtl8366s" },
  909. {},
  910. };
  911. MODULE_DEVICE_TABLE(of, rtl8366s_match);
  912. #endif
  913. static struct platform_driver rtl8366s_driver = {
  914. .driver = {
  915. .name = RTL8366S_DRIVER_NAME,
  916. .owner = THIS_MODULE,
  917. #ifdef CONFIG_OF
  918. .of_match_table = of_match_ptr(rtl8366s_match),
  919. #endif
  920. },
  921. .probe = rtl8366s_probe,
  922. .remove = rtl8366s_remove,
  923. };
  924. static int __init rtl8366s_module_init(void)
  925. {
  926. return platform_driver_register(&rtl8366s_driver);
  927. }
  928. module_init(rtl8366s_module_init);
  929. static void __exit rtl8366s_module_exit(void)
  930. {
  931. platform_driver_unregister(&rtl8366s_driver);
  932. }
  933. module_exit(rtl8366s_module_exit);
  934. MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
  935. MODULE_VERSION(RTL8366S_DRIVER_VER);
  936. MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
  937. MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
  938. MODULE_LICENSE("GPL v2");
  939. MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);