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093-sun6i-fix-PLL-LDO-voltselect.patch 3.0 KB

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  1. From b2b385df5095fff80b4655142f58a2a6801e6c80 Mon Sep 17 00:00:00 2001
  2. From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
  3. Date: Tue, 6 Jan 2015 21:26:44 +0100
  4. Subject: sun6i: Fix and document PLL LDO voltage selection
  5. The PRCM_PLL_CTRL_LDO_OUT_L and PRCM_PLL_CTRL_LDO_OUT_H macros had
  6. their meaning reversed. This is fixed by this change-set. With this
  7. changed, the PRCM_PLL_CTRL_LDO_OUT_L(1370) now becomes self-evident
  8. as setting the voltage to 1.37v (which it had done all along, even
  9. though stating a different target voltage).
  10. After changing the PLL LDO setting, it will take a little while for
  11. the voltage output to settle. A sdelay()-based loop waits the same
  12. order of magnitude as Boot1.
  13. Furthermore, a bit of documentation is added to clarify that the
  14. required setting for the PLL LDO is 1.37v as per the A31 manual.
  15. --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
  16. +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
  17. @@ -24,14 +24,27 @@ void clock_init_safe(void)
  18. struct sunxi_prcm_reg * const prcm =
  19. (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
  20. - /* Set PLL ldo voltage without this PLL6 does not work properly */
  21. + /* Set PLL ldo voltage without this PLL6 does not work properly.
  22. + *
  23. + * As the A31 manual states, that "before enable PLL, PLLVDD
  24. + * LDO should be set to 1.37v", we need to configure this to 2.5v
  25. + * in the "PLL Input Power Select" (0 << 15) and (7 << 16).
  26. + */
  27. clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
  28. PRCM_PLL_CTRL_LDO_KEY);
  29. clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
  30. PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
  31. - PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
  32. + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370) );
  33. clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
  34. + /* Give the PLL LDO voltage setting some time to take hold.
  35. + * Notes:
  36. + * 1) We need to use sdelay() as the timers aren't set up yet.
  37. + * 2) The 100k iterations come from Boot1, which spin's for 100k
  38. + * iterations through a loop.
  39. + */
  40. + sdelay(100000);
  41. +
  42. clock_set_pll1(408000000);
  43. writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  44. --- a/arch/arm/include/asm/arch-sunxi/prcm.h
  45. +++ b/arch/arm/include/asm/arch-sunxi/prcm.h
  46. @@ -111,13 +111,13 @@
  47. #define PRCM_PLL_CTRL_LDO_OUT_MASK \
  48. __PRCM_PLL_CTRL_LDO_OUT(0x7)
  49. /* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
  50. -#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
  51. - __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
  52. #define PRCM_PLL_CTRL_LDO_OUT_H(n) \
  53. + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
  54. +#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
  55. __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
  56. -#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
  57. - __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
  58. #define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
  59. + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
  60. +#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
  61. __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
  62. #define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
  63. #define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)