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102-MIPS-ath79-fix-regression-in-PCI-window-initializati.patch

102-MIPS-ath79-fix-regression-in-PCI-window-initializati.patch 1.7 KB
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  1. From: Felix Fietkau <nbd@nbd.name>
    2. 

  2. Date: Sun, 15 May 2016 13:09:20 +0200
    3. 

  3. Subject: [PATCH] MIPS: ath79: fix regression in PCI window initialization
    4. 

  4. 

  5. ath79_ddr_pci_win_base has the type void __iomem *, so register offsets
    6. 

  6. need to be a multiple of 4.
    7. 

  7. 

  8. Cc: Alban Bedel <albeu@free.fr>
    9. 

  9. Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface")
    10. 

  10. Signed-off-by: Felix Fietkau <nbd@nbd.name>
    11. 

  11. ---
    12. 

  12. 

  13. --- a/arch/mips/ath79/common.c
    14. 

  14. +++ b/arch/mips/ath79/common.c
    15. 

  15. @@ -76,14 +76,14 @@ void ath79_ddr_set_pci_windows(void)
    16. 

  16.  {
    17. 

  17.  	BUG_ON(!ath79_ddr_pci_win_base);
    18. 

  18.  
    19. 

  19. -	__raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0);
    20. 

  20. -	__raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 1);
    21. 

  21. -	__raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 2);
    22. 

  22. -	__raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 3);
    23. 

  23. -	__raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 4);
    24. 

  24. -	__raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 5);
    25. 

  25. -	__raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 6);
    26. 

  26. -	__raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 7);
    27. 

  27. +	__raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0);
    28. 

  28. +	__raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4);
    29. 

  29. +	__raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8);
    30. 

  30. +	__raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc);
    31. 

  31. +	__raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10);
    32. 

  32. +	__raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14);
    33. 

  33. +	__raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18);
    34. 

  34. +	__raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c);
    35. 

  35.  }
    36. 

  36.  EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);
    37. 

  37.  
    38.