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021-bcma-from-4.6.patch 24 KB

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  1. --- a/drivers/bcma/driver_chipcommon.c
  2. +++ b/drivers/bcma/driver_chipcommon.c
  3. @@ -15,6 +15,8 @@
  4. #include <linux/platform_device.h>
  5. #include <linux/bcma/bcma.h>
  6. +static void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
  7. +
  8. static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
  9. u32 mask, u32 value)
  10. {
  11. @@ -113,8 +115,37 @@ int bcma_chipco_watchdog_register(struct
  12. return 0;
  13. }
  14. +static void bcma_core_chipcommon_flash_detect(struct bcma_drv_cc *cc)
  15. +{
  16. + struct bcma_bus *bus = cc->core->bus;
  17. +
  18. + switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
  19. + case BCMA_CC_FLASHT_STSER:
  20. + case BCMA_CC_FLASHT_ATSER:
  21. + bcma_debug(bus, "Found serial flash\n");
  22. + bcma_sflash_init(cc);
  23. + break;
  24. + case BCMA_CC_FLASHT_PARA:
  25. + bcma_debug(bus, "Found parallel flash\n");
  26. + bcma_pflash_init(cc);
  27. + break;
  28. + default:
  29. + bcma_err(bus, "Flash type not supported\n");
  30. + }
  31. +
  32. + if (cc->core->id.rev == 38 ||
  33. + bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
  34. + if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
  35. + bcma_debug(bus, "Found NAND flash\n");
  36. + bcma_nflash_init(cc);
  37. + }
  38. + }
  39. +}
  40. +
  41. void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
  42. {
  43. + struct bcma_bus *bus = cc->core->bus;
  44. +
  45. if (cc->early_setup_done)
  46. return;
  47. @@ -129,6 +160,12 @@ void bcma_core_chipcommon_early_init(str
  48. if (cc->capabilities & BCMA_CC_CAP_PMU)
  49. bcma_pmu_early_init(cc);
  50. + if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC)
  51. + bcma_chipco_serial_init(cc);
  52. +
  53. + if (bus->hosttype == BCMA_HOSTTYPE_SOC)
  54. + bcma_core_chipcommon_flash_detect(cc);
  55. +
  56. cc->early_setup_done = true;
  57. }
  58. @@ -185,11 +222,12 @@ u32 bcma_chipco_watchdog_timer_set(struc
  59. ticks = 2;
  60. else if (ticks > maxt)
  61. ticks = maxt;
  62. - bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
  63. + bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
  64. } else {
  65. struct bcma_bus *bus = cc->core->bus;
  66. if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 &&
  67. + bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 &&
  68. bus->chipinfo.id != BCMA_CHIP_ID_BCM53018)
  69. bcma_core_set_clockmode(cc->core,
  70. ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC);
  71. @@ -314,9 +352,9 @@ u32 bcma_chipco_gpio_pulldown(struct bcm
  72. return res;
  73. }
  74. -#ifdef CONFIG_BCMA_DRIVER_MIPS
  75. -void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
  76. +static void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
  77. {
  78. +#if IS_BUILTIN(CONFIG_BCM47XX)
  79. unsigned int irq;
  80. u32 baud_base;
  81. u32 i;
  82. @@ -358,5 +396,5 @@ void bcma_chipco_serial_init(struct bcma
  83. ports[i].baud_base = baud_base;
  84. ports[i].reg_shift = 0;
  85. }
  86. +#endif /* CONFIG_BCM47XX */
  87. }
  88. -#endif /* CONFIG_BCMA_DRIVER_MIPS */
  89. --- a/drivers/bcma/driver_chipcommon_pmu.c
  90. +++ b/drivers/bcma/driver_chipcommon_pmu.c
  91. @@ -15,44 +15,44 @@
  92. u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
  93. {
  94. - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  95. - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  96. - return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
  97. + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
  98. + bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
  99. + return bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
  100. }
  101. EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
  102. void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
  103. {
  104. - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  105. - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  106. - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
  107. + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
  108. + bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
  109. + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
  110. }
  111. EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
  112. void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
  113. u32 set)
  114. {
  115. - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  116. - bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  117. - bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
  118. + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
  119. + bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_ADDR);
  120. + bcma_pmu_maskset32(cc, BCMA_CC_PMU_PLLCTL_DATA, mask, set);
  121. }
  122. EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
  123. void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
  124. u32 offset, u32 mask, u32 set)
  125. {
  126. - bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
  127. - bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
  128. - bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
  129. + bcma_pmu_write32(cc, BCMA_CC_PMU_CHIPCTL_ADDR, offset);
  130. + bcma_pmu_read32(cc, BCMA_CC_PMU_CHIPCTL_ADDR);
  131. + bcma_pmu_maskset32(cc, BCMA_CC_PMU_CHIPCTL_DATA, mask, set);
  132. }
  133. EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
  134. void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
  135. u32 set)
  136. {
  137. - bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
  138. - bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
  139. - bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
  140. + bcma_pmu_write32(cc, BCMA_CC_PMU_REGCTL_ADDR, offset);
  141. + bcma_pmu_read32(cc, BCMA_CC_PMU_REGCTL_ADDR);
  142. + bcma_pmu_maskset32(cc, BCMA_CC_PMU_REGCTL_DATA, mask, set);
  143. }
  144. EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
  145. @@ -60,18 +60,18 @@ static u32 bcma_pmu_xtalfreq(struct bcma
  146. {
  147. u32 ilp_ctl, alp_hz;
  148. - if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
  149. + if (!(bcma_pmu_read32(cc, BCMA_CC_PMU_STAT) &
  150. BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
  151. return 0;
  152. - bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
  153. - BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
  154. + bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
  155. + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
  156. usleep_range(1000, 2000);
  157. - ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
  158. + ilp_ctl = bcma_pmu_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
  159. ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
  160. - bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
  161. + bcma_pmu_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
  162. alp_hz = ilp_ctl * 32768 / 4;
  163. return (alp_hz + 50000) / 100000 * 100;
  164. @@ -127,8 +127,8 @@ static void bcma_pmu2_pll_init0(struct b
  165. mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
  166. BCMA_RES_4314_MACPHY_CLK_AVAIL);
  167. - bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
  168. - bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
  169. + bcma_pmu_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
  170. + bcma_pmu_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
  171. bcma_wait_value(cc->core, BCMA_CLKCTLST,
  172. BCMA_CLKCTLST_HAVEHT, 0, 20000);
  173. break;
  174. @@ -140,7 +140,7 @@ static void bcma_pmu2_pll_init0(struct b
  175. /* Flush */
  176. if (cc->pmu.rev >= 2)
  177. - bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
  178. + bcma_pmu_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
  179. /* TODO: Do we need to update OTP? */
  180. }
  181. @@ -195,9 +195,9 @@ static void bcma_pmu_resources_init(stru
  182. /* Set the resource masks. */
  183. if (min_msk)
  184. - bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
  185. + bcma_pmu_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
  186. if (max_msk)
  187. - bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
  188. + bcma_pmu_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
  189. /*
  190. * Add some delay; allow resources to come up and settle.
  191. @@ -269,23 +269,33 @@ static void bcma_pmu_workarounds(struct
  192. void bcma_pmu_early_init(struct bcma_drv_cc *cc)
  193. {
  194. + struct bcma_bus *bus = cc->core->bus;
  195. u32 pmucap;
  196. - pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
  197. + if (cc->core->id.rev >= 35 &&
  198. + cc->capabilities_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {
  199. + cc->pmu.core = bcma_find_core(bus, BCMA_CORE_PMU);
  200. + if (!cc->pmu.core)
  201. + bcma_warn(bus, "Couldn't find expected PMU core");
  202. + }
  203. + if (!cc->pmu.core)
  204. + cc->pmu.core = cc->core;
  205. +
  206. + pmucap = bcma_pmu_read32(cc, BCMA_CC_PMU_CAP);
  207. cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
  208. - bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
  209. - cc->pmu.rev, pmucap);
  210. + bcma_debug(bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
  211. + pmucap);
  212. }
  213. void bcma_pmu_init(struct bcma_drv_cc *cc)
  214. {
  215. if (cc->pmu.rev == 1)
  216. - bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
  217. - ~BCMA_CC_PMU_CTL_NOILPONW);
  218. + bcma_pmu_mask32(cc, BCMA_CC_PMU_CTL,
  219. + ~BCMA_CC_PMU_CTL_NOILPONW);
  220. else
  221. - bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
  222. - BCMA_CC_PMU_CTL_NOILPONW);
  223. + bcma_pmu_set32(cc, BCMA_CC_PMU_CTL,
  224. + BCMA_CC_PMU_CTL_NOILPONW);
  225. bcma_pmu_pll_init(cc);
  226. bcma_pmu_resources_init(cc);
  227. @@ -472,8 +482,8 @@ u32 bcma_pmu_get_cpu_clock(struct bcma_d
  228. static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
  229. u32 value)
  230. {
  231. - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  232. - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
  233. + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR, offset);
  234. + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, value);
  235. }
  236. void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
  237. @@ -497,20 +507,20 @@ void bcma_pmu_spuravoid_pllupdate(struct
  238. bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
  239. /* RMW only the P1 divider */
  240. - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
  241. + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
  242. BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
  243. - tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
  244. + tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
  245. tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
  246. tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
  247. - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
  248. + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
  249. /* RMW only the int feedback divider */
  250. - bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
  251. + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_ADDR,
  252. BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
  253. - tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
  254. + tmp = bcma_pmu_read32(cc, BCMA_CC_PMU_PLLCTL_DATA);
  255. tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
  256. tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
  257. - bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
  258. + bcma_pmu_write32(cc, BCMA_CC_PMU_PLLCTL_DATA, tmp);
  259. tmp = BCMA_CC_PMU_CTL_PLL_UPD;
  260. break;
  261. @@ -646,7 +656,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
  262. break;
  263. }
  264. - tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
  265. - bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
  266. + tmp |= bcma_pmu_read32(cc, BCMA_CC_PMU_CTL);
  267. + bcma_pmu_write32(cc, BCMA_CC_PMU_CTL, tmp);
  268. }
  269. EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
  270. --- a/drivers/bcma/driver_chipcommon_sflash.c
  271. +++ b/drivers/bcma/driver_chipcommon_sflash.c
  272. @@ -38,6 +38,7 @@ static const struct bcma_sflash_tbl_e bc
  273. { "M25P32", 0x15, 0x10000, 64, },
  274. { "M25P64", 0x16, 0x10000, 128, },
  275. { "M25FL128", 0x17, 0x10000, 256, },
  276. + { "MX25L25635F", 0x18, 0x10000, 512, },
  277. { NULL },
  278. };
  279. --- a/drivers/bcma/scan.c
  280. +++ b/drivers/bcma/scan.c
  281. @@ -98,6 +98,9 @@ static const struct bcma_device_id_name
  282. { BCMA_CORE_SHIM, "SHIM" },
  283. { BCMA_CORE_PCIE2, "PCIe Gen2" },
  284. { BCMA_CORE_ARM_CR4, "ARM CR4" },
  285. + { BCMA_CORE_GCI, "GCI" },
  286. + { BCMA_CORE_CMEM, "CNDS DDR2/3 memory controller" },
  287. + { BCMA_CORE_ARM_CA7, "ARM CA7" },
  288. { BCMA_CORE_DEFAULT, "Default" },
  289. };
  290. @@ -315,6 +318,8 @@ static int bcma_get_next_core(struct bcm
  291. switch (core->id.id) {
  292. case BCMA_CORE_4706_MAC_GBIT_COMMON:
  293. case BCMA_CORE_NS_CHIPCOMMON_B:
  294. + case BCMA_CORE_PMU:
  295. + case BCMA_CORE_GCI:
  296. /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
  297. break;
  298. default:
  299. --- a/drivers/net/wireless/b43/main.c
  300. +++ b/drivers/net/wireless/b43/main.c
  301. @@ -1215,10 +1215,10 @@ void b43_wireless_core_phy_pll_reset(str
  302. case B43_BUS_BCMA:
  303. bcma_cc = &dev->dev->bdev->bus->drv_cc;
  304. - bcma_cc_write32(bcma_cc, BCMA_CC_CHIPCTL_ADDR, 0);
  305. - bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
  306. - bcma_cc_set32(bcma_cc, BCMA_CC_CHIPCTL_DATA, 0x4);
  307. - bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4);
  308. + bcma_cc_write32(bcma_cc, BCMA_CC_PMU_CHIPCTL_ADDR, 0);
  309. + bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
  310. + bcma_cc_set32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, 0x4);
  311. + bcma_cc_mask32(bcma_cc, BCMA_CC_PMU_CHIPCTL_DATA, ~0x4);
  312. break;
  313. #endif
  314. #ifdef CONFIG_B43_SSB
  315. --- a/include/linux/bcma/bcma.h
  316. +++ b/include/linux/bcma/bcma.h
  317. @@ -151,6 +151,8 @@ struct bcma_host_ops {
  318. #define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
  319. #define BCMA_CORE_USB30_DEV 0x83D
  320. #define BCMA_CORE_ARM_CR4 0x83E
  321. +#define BCMA_CORE_GCI 0x840
  322. +#define BCMA_CORE_CMEM 0x846 /* CNDS DDR2/3 memory controller */
  323. #define BCMA_CORE_ARM_CA7 0x847
  324. #define BCMA_CORE_SYS_MEM 0x849
  325. #define BCMA_CORE_DEFAULT 0xFFF
  326. @@ -200,6 +202,7 @@ struct bcma_host_ops {
  327. #define BCMA_PKG_ID_BCM4707 1
  328. #define BCMA_PKG_ID_BCM4708 2
  329. #define BCMA_PKG_ID_BCM4709 0
  330. +#define BCMA_CHIP_ID_BCM47094 53030
  331. #define BCMA_CHIP_ID_BCM53018 53018
  332. /* Board types (on PCI usually equals to the subsystem dev id) */
  333. --- a/include/linux/bcma/bcma_driver_chipcommon.h
  334. +++ b/include/linux/bcma/bcma_driver_chipcommon.h
  335. @@ -217,6 +217,11 @@
  336. #define BCMA_CC_CLKDIV_JTAG_SHIFT 8
  337. #define BCMA_CC_CLKDIV_UART 0x000000FF
  338. #define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */
  339. +#define BCMA_CC_CAP_EXT_SECI_PRESENT 0x00000001
  340. +#define BCMA_CC_CAP_EXT_GSIO_PRESENT 0x00000002
  341. +#define BCMA_CC_CAP_EXT_GCI_PRESENT 0x00000004
  342. +#define BCMA_CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /* UART present */
  343. +#define BCMA_CC_CAP_EXT_AOB_PRESENT 0x00000040
  344. #define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */
  345. #define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
  346. #define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
  347. @@ -351,12 +356,12 @@
  348. #define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
  349. #define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
  350. #define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
  351. -#define BCMA_CC_CHIPCTL_ADDR 0x0650
  352. -#define BCMA_CC_CHIPCTL_DATA 0x0654
  353. -#define BCMA_CC_REGCTL_ADDR 0x0658
  354. -#define BCMA_CC_REGCTL_DATA 0x065C
  355. -#define BCMA_CC_PLLCTL_ADDR 0x0660
  356. -#define BCMA_CC_PLLCTL_DATA 0x0664
  357. +#define BCMA_CC_PMU_CHIPCTL_ADDR 0x0650
  358. +#define BCMA_CC_PMU_CHIPCTL_DATA 0x0654
  359. +#define BCMA_CC_PMU_REGCTL_ADDR 0x0658
  360. +#define BCMA_CC_PMU_REGCTL_DATA 0x065C
  361. +#define BCMA_CC_PMU_PLLCTL_ADDR 0x0660
  362. +#define BCMA_CC_PMU_PLLCTL_DATA 0x0664
  363. #define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
  364. #define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
  365. #define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
  366. @@ -566,17 +571,16 @@
  367. * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
  368. */
  369. struct bcma_chipcommon_pmu {
  370. + struct bcma_device *core; /* Can be separated core or just ChipCommon one */
  371. u8 rev; /* PMU revision */
  372. u32 crystalfreq; /* The active crystal frequency (in kHz) */
  373. };
  374. -#ifdef CONFIG_BCMA_DRIVER_MIPS
  375. +#ifdef CONFIG_BCMA_PFLASH
  376. struct bcma_pflash {
  377. bool present;
  378. - u8 buswidth;
  379. - u32 window;
  380. - u32 window_size;
  381. };
  382. +#endif
  383. #ifdef CONFIG_BCMA_SFLASH
  384. struct bcma_sflash {
  385. @@ -602,6 +606,7 @@ struct bcma_nflash {
  386. };
  387. #endif
  388. +#ifdef CONFIG_BCMA_DRIVER_MIPS
  389. struct bcma_serial_port {
  390. void *regs;
  391. unsigned long clockspeed;
  392. @@ -621,8 +626,9 @@ struct bcma_drv_cc {
  393. /* Fast Powerup Delay constant */
  394. u16 fast_pwrup_delay;
  395. struct bcma_chipcommon_pmu pmu;
  396. -#ifdef CONFIG_BCMA_DRIVER_MIPS
  397. +#ifdef CONFIG_BCMA_PFLASH
  398. struct bcma_pflash pflash;
  399. +#endif
  400. #ifdef CONFIG_BCMA_SFLASH
  401. struct bcma_sflash sflash;
  402. #endif
  403. @@ -630,6 +636,7 @@ struct bcma_drv_cc {
  404. struct bcma_nflash nflash;
  405. #endif
  406. +#ifdef CONFIG_BCMA_DRIVER_MIPS
  407. int nr_serial_ports;
  408. struct bcma_serial_port serial_ports[4];
  409. #endif /* CONFIG_BCMA_DRIVER_MIPS */
  410. @@ -662,6 +669,19 @@ struct bcma_drv_cc_b {
  411. #define bcma_cc_maskset32(cc, offset, mask, set) \
  412. bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
  413. +/* PMU registers access */
  414. +#define bcma_pmu_read32(cc, offset) \
  415. + bcma_read32((cc)->pmu.core, offset)
  416. +#define bcma_pmu_write32(cc, offset, val) \
  417. + bcma_write32((cc)->pmu.core, offset, val)
  418. +
  419. +#define bcma_pmu_mask32(cc, offset, mask) \
  420. + bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) & (mask))
  421. +#define bcma_pmu_set32(cc, offset, set) \
  422. + bcma_pmu_write32(cc, offset, bcma_pmu_read32(cc, offset) | (set))
  423. +#define bcma_pmu_maskset32(cc, offset, mask, set) \
  424. + bcma_pmu_write32(cc, offset, (bcma_pmu_read32(cc, offset) & (mask)) | (set))
  425. +
  426. extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
  427. extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
  428. --- a/drivers/bcma/bcma_private.h
  429. +++ b/drivers/bcma/bcma_private.h
  430. @@ -45,10 +45,6 @@ int bcma_sprom_get(struct bcma_bus *bus)
  431. void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
  432. void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
  433. void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
  434. -#ifdef CONFIG_BCMA_DRIVER_MIPS
  435. -void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
  436. -extern struct platform_device bcma_pflash_dev;
  437. -#endif /* CONFIG_BCMA_DRIVER_MIPS */
  438. /* driver_chipcommon_b.c */
  439. int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
  440. @@ -60,6 +56,21 @@ void bcma_pmu_init(struct bcma_drv_cc *c
  441. u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
  442. u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
  443. +/**************************************************
  444. + * driver_chipcommon_sflash.c
  445. + **************************************************/
  446. +
  447. +#ifdef CONFIG_BCMA_PFLASH
  448. +extern struct platform_device bcma_pflash_dev;
  449. +int bcma_pflash_init(struct bcma_drv_cc *cc);
  450. +#else
  451. +static inline int bcma_pflash_init(struct bcma_drv_cc *cc)
  452. +{
  453. + bcma_err(cc->core->bus, "Parallel flash not supported\n");
  454. + return 0;
  455. +}
  456. +#endif /* CONFIG_BCMA_PFLASH */
  457. +
  458. #ifdef CONFIG_BCMA_SFLASH
  459. /* driver_chipcommon_sflash.c */
  460. int bcma_sflash_init(struct bcma_drv_cc *cc);
  461. --- a/drivers/bcma/driver_gpio.c
  462. +++ b/drivers/bcma/driver_gpio.c
  463. @@ -197,6 +197,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c
  464. case BCMA_CHIP_ID_BCM4707:
  465. case BCMA_CHIP_ID_BCM5357:
  466. case BCMA_CHIP_ID_BCM53572:
  467. + case BCMA_CHIP_ID_BCM47094:
  468. chip->ngpio = 32;
  469. break;
  470. default:
  471. --- a/drivers/bcma/driver_mips.c
  472. +++ b/drivers/bcma/driver_mips.c
  473. @@ -14,8 +14,6 @@
  474. #include <linux/bcma/bcma.h>
  475. -#include <linux/mtd/physmap.h>
  476. -#include <linux/platform_device.h>
  477. #include <linux/serial.h>
  478. #include <linux/serial_core.h>
  479. #include <linux/serial_reg.h>
  480. @@ -32,26 +30,6 @@ enum bcma_boot_dev {
  481. BCMA_BOOT_DEV_NAND,
  482. };
  483. -static const char * const part_probes[] = { "bcm47xxpart", NULL };
  484. -
  485. -static struct physmap_flash_data bcma_pflash_data = {
  486. - .part_probe_types = part_probes,
  487. -};
  488. -
  489. -static struct resource bcma_pflash_resource = {
  490. - .name = "bcma_pflash",
  491. - .flags = IORESOURCE_MEM,
  492. -};
  493. -
  494. -struct platform_device bcma_pflash_dev = {
  495. - .name = "physmap-flash",
  496. - .dev = {
  497. - .platform_data = &bcma_pflash_data,
  498. - },
  499. - .resource = &bcma_pflash_resource,
  500. - .num_resources = 1,
  501. -};
  502. -
  503. /* The 47162a0 hangs when reading MIPS DMP registers registers */
  504. static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
  505. {
  506. @@ -272,48 +250,11 @@ static enum bcma_boot_dev bcma_boot_dev(
  507. return BCMA_BOOT_DEV_SERIAL;
  508. }
  509. -static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
  510. +static void bcma_core_mips_nvram_init(struct bcma_drv_mips *mcore)
  511. {
  512. struct bcma_bus *bus = mcore->core->bus;
  513. - struct bcma_drv_cc *cc = &bus->drv_cc;
  514. - struct bcma_pflash *pflash = &cc->pflash;
  515. enum bcma_boot_dev boot_dev;
  516. - switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
  517. - case BCMA_CC_FLASHT_STSER:
  518. - case BCMA_CC_FLASHT_ATSER:
  519. - bcma_debug(bus, "Found serial flash\n");
  520. - bcma_sflash_init(cc);
  521. - break;
  522. - case BCMA_CC_FLASHT_PARA:
  523. - bcma_debug(bus, "Found parallel flash\n");
  524. - pflash->present = true;
  525. - pflash->window = BCMA_SOC_FLASH2;
  526. - pflash->window_size = BCMA_SOC_FLASH2_SZ;
  527. -
  528. - if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
  529. - BCMA_CC_FLASH_CFG_DS) == 0)
  530. - pflash->buswidth = 1;
  531. - else
  532. - pflash->buswidth = 2;
  533. -
  534. - bcma_pflash_data.width = pflash->buswidth;
  535. - bcma_pflash_resource.start = pflash->window;
  536. - bcma_pflash_resource.end = pflash->window + pflash->window_size;
  537. -
  538. - break;
  539. - default:
  540. - bcma_err(bus, "Flash type not supported\n");
  541. - }
  542. -
  543. - if (cc->core->id.rev == 38 ||
  544. - bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
  545. - if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
  546. - bcma_debug(bus, "Found NAND flash\n");
  547. - bcma_nflash_init(cc);
  548. - }
  549. - }
  550. -
  551. /* Determine flash type this SoC boots from */
  552. boot_dev = bcma_boot_dev(bus);
  553. switch (boot_dev) {
  554. @@ -337,13 +278,10 @@ static void bcma_core_mips_flash_detect(
  555. void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
  556. {
  557. - struct bcma_bus *bus = mcore->core->bus;
  558. -
  559. if (mcore->early_setup_done)
  560. return;
  561. - bcma_chipco_serial_init(&bus->drv_cc);
  562. - bcma_core_mips_flash_detect(mcore);
  563. + bcma_core_mips_nvram_init(mcore);
  564. mcore->early_setup_done = true;
  565. }
  566. --- a/drivers/bcma/host_pci.c
  567. +++ b/drivers/bcma/host_pci.c
  568. @@ -294,7 +294,8 @@ static const struct pci_device_id bcma_p
  569. { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
  570. { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
  571. { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4360) },
  572. - { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
  573. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_DELL, 0x0016) },
  574. + { PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, 0x4365, PCI_VENDOR_ID_FOXCONN, 0xe092) },
  575. { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a0) },
  576. { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
  577. { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
  578. --- a/drivers/bcma/Kconfig
  579. +++ b/drivers/bcma/Kconfig
  580. @@ -70,6 +70,11 @@ config BCMA_DRIVER_MIPS
  581. If unsure, say N
  582. +config BCMA_PFLASH
  583. + bool
  584. + depends on BCMA_DRIVER_MIPS
  585. + default y
  586. +
  587. config BCMA_SFLASH
  588. bool
  589. depends on BCMA_DRIVER_MIPS
  590. --- a/drivers/bcma/Makefile
  591. +++ b/drivers/bcma/Makefile
  592. @@ -1,6 +1,7 @@
  593. bcma-y += main.o scan.o core.o sprom.o
  594. bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
  595. bcma-y += driver_chipcommon_b.o
  596. +bcma-$(CONFIG_BCMA_PFLASH) += driver_chipcommon_pflash.o
  597. bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
  598. bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
  599. bcma-$(CONFIG_BCMA_DRIVER_PCI) += driver_pci.o
  600. --- /dev/null
  601. +++ b/drivers/bcma/driver_chipcommon_pflash.c
  602. @@ -0,0 +1,49 @@
  603. +/*
  604. + * Broadcom specific AMBA
  605. + * ChipCommon parallel flash
  606. + *
  607. + * Licensed under the GNU/GPL. See COPYING for details.
  608. + */
  609. +
  610. +#include "bcma_private.h"
  611. +
  612. +#include <linux/bcma/bcma.h>
  613. +#include <linux/mtd/physmap.h>
  614. +#include <linux/platform_device.h>
  615. +
  616. +static const char * const part_probes[] = { "bcm47xxpart", NULL };
  617. +
  618. +static struct physmap_flash_data bcma_pflash_data = {
  619. + .part_probe_types = part_probes,
  620. +};
  621. +
  622. +static struct resource bcma_pflash_resource = {
  623. + .name = "bcma_pflash",
  624. + .flags = IORESOURCE_MEM,
  625. +};
  626. +
  627. +struct platform_device bcma_pflash_dev = {
  628. + .name = "physmap-flash",
  629. + .dev = {
  630. + .platform_data = &bcma_pflash_data,
  631. + },
  632. + .resource = &bcma_pflash_resource,
  633. + .num_resources = 1,
  634. +};
  635. +
  636. +int bcma_pflash_init(struct bcma_drv_cc *cc)
  637. +{
  638. + struct bcma_pflash *pflash = &cc->pflash;
  639. +
  640. + pflash->present = true;
  641. +
  642. + if (!(bcma_read32(cc->core, BCMA_CC_FLASH_CFG) & BCMA_CC_FLASH_CFG_DS))
  643. + bcma_pflash_data.width = 1;
  644. + else
  645. + bcma_pflash_data.width = 2;
  646. +
  647. + bcma_pflash_resource.start = BCMA_SOC_FLASH2;
  648. + bcma_pflash_resource.end = BCMA_SOC_FLASH2 + BCMA_SOC_FLASH2_SZ;
  649. +
  650. + return 0;
  651. +}
  652. --- a/drivers/bcma/main.c
  653. +++ b/drivers/bcma/main.c
  654. @@ -136,7 +136,6 @@ static bool bcma_is_core_needed_early(u1
  655. return false;
  656. }
  657. -#if defined(CONFIG_OF) && defined(CONFIG_OF_ADDRESS)
  658. static struct device_node *bcma_of_find_child_device(struct platform_device *parent,
  659. struct bcma_device *core)
  660. {
  661. @@ -184,7 +183,7 @@ static unsigned int bcma_of_get_irq(stru
  662. struct of_phandle_args out_irq;
  663. int ret;
  664. - if (!parent || !parent->dev.of_node)
  665. + if (!IS_ENABLED(CONFIG_OF_IRQ) || !parent || !parent->dev.of_node)
  666. return 0;
  667. ret = bcma_of_irq_parse(parent, core, &out_irq, num);
  668. @@ -202,23 +201,15 @@ static void bcma_of_fill_device(struct p
  669. {
  670. struct device_node *node;
  671. + if (!IS_ENABLED(CONFIG_OF_IRQ))
  672. + return;
  673. +
  674. node = bcma_of_find_child_device(parent, core);
  675. if (node)
  676. core->dev.of_node = node;
  677. core->irq = bcma_of_get_irq(parent, core, 0);
  678. }
  679. -#else
  680. -static void bcma_of_fill_device(struct platform_device *parent,
  681. - struct bcma_device *core)
  682. -{
  683. -}
  684. -static inline unsigned int bcma_of_get_irq(struct platform_device *parent,
  685. - struct bcma_device *core, int num)
  686. -{
  687. - return 0;
  688. -}
  689. -#endif /* CONFIG_OF */
  690. unsigned int bcma_core_irq(struct bcma_device *core, int num)
  691. {
  692. @@ -350,7 +341,7 @@ static int bcma_register_devices(struct
  693. bcma_register_core(bus, core);
  694. }
  695. -#ifdef CONFIG_BCMA_DRIVER_MIPS
  696. +#ifdef CONFIG_BCMA_PFLASH
  697. if (bus->drv_cc.pflash.present) {
  698. err = platform_device_register(&bcma_pflash_dev);
  699. if (err)