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0004-MIPS-ralink-add-MT7621-pcie-driver.patch 33 KB

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  1. From fec11d4e8dc5cc79bcd7c8fd55038ac21ac39965 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Sun, 16 Mar 2014 05:22:39 +0000
  4. Subject: [PATCH 04/53] MIPS: ralink: add MT7621 pcie driver
  5. Signed-off-by: John Crispin <blogic@openwrt.org>
  6. ---
  7. arch/mips/pci/Makefile | 1 +
  8. arch/mips/pci/pci-mt7621.c | 813 ++++++++++++++++++++++++++++++++++++++++++++
  9. 2 files changed, 814 insertions(+)
  10. create mode 100644 arch/mips/pci/pci-mt7621.c
  11. --- a/arch/mips/pci/Makefile
  12. +++ b/arch/mips/pci/Makefile
  13. @@ -43,6 +43,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
  14. obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
  15. obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
  16. obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
  17. +obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
  18. obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
  19. obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
  20. obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
  21. --- /dev/null
  22. +++ b/arch/mips/pci/pci-mt7621.c
  23. @@ -0,0 +1,832 @@
  24. +/**************************************************************************
  25. + *
  26. + * BRIEF MODULE DESCRIPTION
  27. + * PCI init for Ralink RT2880 solution
  28. + *
  29. + * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
  30. + *
  31. + * This program is free software; you can redistribute it and/or modify it
  32. + * under the terms of the GNU General Public License as published by the
  33. + * Free Software Foundation; either version 2 of the License, or (at your
  34. + * option) any later version.
  35. + *
  36. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  37. + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  38. + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  39. + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  40. + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  41. + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  42. + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  43. + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  44. + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  45. + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  46. + *
  47. + * You should have received a copy of the GNU General Public License along
  48. + * with this program; if not, write to the Free Software Foundation, Inc.,
  49. + * 675 Mass Ave, Cambridge, MA 02139, USA.
  50. + *
  51. + *
  52. + **************************************************************************
  53. + * May 2007 Bruce Chang
  54. + * Initial Release
  55. + *
  56. + * May 2009 Bruce Chang
  57. + * support RT2880/RT3883 PCIe
  58. + *
  59. + * May 2011 Bruce Chang
  60. + * support RT6855/MT7620 PCIe
  61. + *
  62. + **************************************************************************
  63. + */
  64. +
  65. +#include <linux/types.h>
  66. +#include <linux/pci.h>
  67. +#include <linux/kernel.h>
  68. +#include <linux/slab.h>
  69. +#include <linux/version.h>
  70. +#include <asm/pci.h>
  71. +#include <asm/io.h>
  72. +#include <asm/mips-cm.h>
  73. +#include <linux/init.h>
  74. +#include <linux/module.h>
  75. +#include <linux/delay.h>
  76. +#include <linux/of.h>
  77. +#include <linux/of_pci.h>
  78. +#include <linux/platform_device.h>
  79. +
  80. +#include <ralink_regs.h>
  81. +
  82. +extern void pcie_phy_init(void);
  83. +extern void chk_phy_pll(void);
  84. +
  85. +/*
  86. + * These functions and structures provide the BIOS scan and mapping of the PCI
  87. + * devices.
  88. + */
  89. +
  90. +#define CONFIG_PCIE_PORT0
  91. +#define CONFIG_PCIE_PORT1
  92. +#define CONFIG_PCIE_PORT2
  93. +#define RALINK_PCIE0_CLK_EN (1<<24)
  94. +#define RALINK_PCIE1_CLK_EN (1<<25)
  95. +#define RALINK_PCIE2_CLK_EN (1<<26)
  96. +
  97. +#define RALINK_PCI_CONFIG_ADDR 0x20
  98. +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
  99. +#define SURFBOARDINT_PCIE0 11 /* PCIE0 */
  100. +#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0
  101. +#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1
  102. +#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2
  103. +#define SURFBOARDINT_PCIE1 31 /* PCIE1 */
  104. +#define SURFBOARDINT_PCIE2 32 /* PCIE2 */
  105. +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
  106. +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
  107. +#define RALINK_PCIE0_RST (1<<24)
  108. +#define RALINK_PCIE1_RST (1<<25)
  109. +#define RALINK_PCIE2_RST (1<<26)
  110. +#define RALINK_SYSCTL_BASE 0xBE000000
  111. +
  112. +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
  113. +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
  114. +#define RALINK_PCI_BASE 0xBE140000
  115. +
  116. +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
  117. +#define RT6855_PCIE0_OFFSET 0x2000
  118. +#define RT6855_PCIE1_OFFSET 0x3000
  119. +#define RT6855_PCIE2_OFFSET 0x4000
  120. +
  121. +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
  122. +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
  123. +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
  124. +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
  125. +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
  126. +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
  127. +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
  128. +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
  129. +
  130. +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
  131. +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
  132. +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
  133. +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
  134. +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
  135. +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
  136. +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
  137. +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
  138. +
  139. +#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
  140. +#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
  141. +#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
  142. +#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
  143. +#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
  144. +#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
  145. +#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
  146. +#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
  147. +
  148. +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
  149. +#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
  150. +
  151. +
  152. +#define MV_WRITE(ofs, data) \
  153. + *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
  154. +#define MV_READ(ofs, data) \
  155. + *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
  156. +#define MV_READ_DATA(ofs) \
  157. + le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
  158. +
  159. +#define MV_WRITE_16(ofs, data) \
  160. + *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
  161. +#define MV_READ_16(ofs, data) \
  162. + *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
  163. +
  164. +#define MV_WRITE_8(ofs, data) \
  165. + *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
  166. +#define MV_READ_8(ofs, data) \
  167. + *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
  168. +
  169. +
  170. +
  171. +#define RALINK_PCI_MM_MAP_BASE 0x60000000
  172. +#define RALINK_PCI_IO_MAP_BASE 0x1e160000
  173. +
  174. +#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
  175. +#define GPIO_PERST
  176. +#define ASSERT_SYSRST_PCIE(val) do { \
  177. + if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
  178. + RALINK_RSTCTRL |= val; \
  179. + else \
  180. + RALINK_RSTCTRL &= ~val; \
  181. + } while(0)
  182. +#define DEASSERT_SYSRST_PCIE(val) do { \
  183. + if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
  184. + RALINK_RSTCTRL &= ~val; \
  185. + else \
  186. + RALINK_RSTCTRL |= val; \
  187. + } while(0)
  188. +#define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
  189. +#define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
  190. +#define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
  191. +#define RALINK_GPIOMODE *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
  192. +#define RALINK_PCIE_CLK_GEN *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
  193. +#define RALINK_PCIE_CLK_GEN1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
  194. +#define PPLL_CFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
  195. +#define PPLL_DRV *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
  196. +//RALINK_SYSCFG1 bit
  197. +#define RALINK_PCI_HOST_MODE_EN (1<<7)
  198. +#define RALINK_PCIE_RC_MODE_EN (1<<8)
  199. +//RALINK_RSTCTRL bit
  200. +#define RALINK_PCIE_RST (1<<23)
  201. +#define RALINK_PCI_RST (1<<24)
  202. +//RALINK_CLKCFG1 bit
  203. +#define RALINK_PCI_CLK_EN (1<<19)
  204. +#define RALINK_PCIE_CLK_EN (1<<21)
  205. +//RALINK_GPIOMODE bit
  206. +#define PCI_SLOTx2 (1<<11)
  207. +#define PCI_SLOTx1 (2<<11)
  208. +//MTK PCIE PLL bit
  209. +#define PDRV_SW_SET (1<<31)
  210. +#define LC_CKDRVPD_ (1<<19)
  211. +
  212. +#define MEMORY_BASE 0x0
  213. +static int pcie_link_status = 0;
  214. +
  215. +#define PCI_ACCESS_READ_1 0
  216. +#define PCI_ACCESS_READ_2 1
  217. +#define PCI_ACCESS_READ_4 2
  218. +#define PCI_ACCESS_WRITE_1 3
  219. +#define PCI_ACCESS_WRITE_2 4
  220. +#define PCI_ACCESS_WRITE_4 5
  221. +
  222. +static int config_access(unsigned char access_type, struct pci_bus *bus,
  223. + unsigned int devfn, unsigned int where, u32 * data)
  224. +{
  225. + unsigned int slot = PCI_SLOT(devfn);
  226. + u8 func = PCI_FUNC(devfn);
  227. + uint32_t address_reg, data_reg;
  228. + unsigned int address;
  229. +
  230. + address_reg = RALINK_PCI_CONFIG_ADDR;
  231. + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
  232. +
  233. + address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
  234. + MV_WRITE(address_reg, address);
  235. +
  236. + switch(access_type) {
  237. + case PCI_ACCESS_WRITE_1:
  238. + MV_WRITE_8(data_reg+(where&0x3), *data);
  239. + break;
  240. + case PCI_ACCESS_WRITE_2:
  241. + MV_WRITE_16(data_reg+(where&0x3), *data);
  242. + break;
  243. + case PCI_ACCESS_WRITE_4:
  244. + MV_WRITE(data_reg, *data);
  245. + break;
  246. + case PCI_ACCESS_READ_1:
  247. + MV_READ_8( data_reg+(where&0x3), data);
  248. + break;
  249. + case PCI_ACCESS_READ_2:
  250. + MV_READ_16(data_reg+(where&0x3), data);
  251. + break;
  252. + case PCI_ACCESS_READ_4:
  253. + MV_READ(data_reg, data);
  254. + break;
  255. + default:
  256. + printk("no specify access type\n");
  257. + break;
  258. + }
  259. + return 0;
  260. +}
  261. +
  262. +static int
  263. +read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
  264. +{
  265. + return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
  266. +}
  267. +
  268. +static int
  269. +read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
  270. +{
  271. + return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
  272. +}
  273. +
  274. +static int
  275. +read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
  276. +{
  277. + return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
  278. +}
  279. +
  280. +static int
  281. +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
  282. +{
  283. + if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
  284. + return -1;
  285. +
  286. + return PCIBIOS_SUCCESSFUL;
  287. +}
  288. +
  289. +static int
  290. +write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
  291. +{
  292. + if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
  293. + return -1;
  294. +
  295. + return PCIBIOS_SUCCESSFUL;
  296. +}
  297. +
  298. +static int
  299. +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
  300. +{
  301. + if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
  302. + return -1;
  303. +
  304. + return PCIBIOS_SUCCESSFUL;
  305. +}
  306. +
  307. +
  308. +static int
  309. +pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
  310. +{
  311. + switch (size) {
  312. + case 1:
  313. + return read_config_byte(bus, devfn, where, (u8 *) val);
  314. + case 2:
  315. + return read_config_word(bus, devfn, where, (u16 *) val);
  316. + default:
  317. + return read_config_dword(bus, devfn, where, val);
  318. + }
  319. +}
  320. +
  321. +static int
  322. +pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
  323. +{
  324. + switch (size) {
  325. + case 1:
  326. + return write_config_byte(bus, devfn, where, (u8) val);
  327. + case 2:
  328. + return write_config_word(bus, devfn, where, (u16) val);
  329. + default:
  330. + return write_config_dword(bus, devfn, where, val);
  331. + }
  332. +}
  333. +
  334. +struct pci_ops mt7621_pci_ops= {
  335. + .read = pci_config_read,
  336. + .write = pci_config_write,
  337. +};
  338. +
  339. +static struct resource mt7621_res_pci_mem1 = {
  340. + .name = "PCI MEM1",
  341. + .start = RALINK_PCI_MM_MAP_BASE,
  342. + .end = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
  343. + .flags = IORESOURCE_MEM,
  344. +};
  345. +static struct resource mt7621_res_pci_io1 = {
  346. + .name = "PCI I/O1",
  347. + .start = RALINK_PCI_IO_MAP_BASE,
  348. + .end = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
  349. + .flags = IORESOURCE_IO,
  350. +};
  351. +
  352. +static struct pci_controller mt7621_controller = {
  353. + .pci_ops = &mt7621_pci_ops,
  354. + .mem_resource = &mt7621_res_pci_mem1,
  355. + .io_resource = &mt7621_res_pci_io1,
  356. + .mem_offset = 0x00000000UL,
  357. + .io_offset = 0x00000000UL,
  358. + .io_map_base = 0xa0000000,
  359. +};
  360. +
  361. +static void
  362. +read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
  363. +{
  364. + unsigned int address_reg, data_reg, address;
  365. +
  366. + address_reg = RALINK_PCI_CONFIG_ADDR;
  367. + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
  368. + address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
  369. + MV_WRITE(address_reg, address);
  370. + MV_READ(data_reg, val);
  371. + return;
  372. +}
  373. +
  374. +static void
  375. +write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
  376. +{
  377. + unsigned int address_reg, data_reg, address;
  378. +
  379. + address_reg = RALINK_PCI_CONFIG_ADDR;
  380. + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
  381. + address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
  382. + MV_WRITE(address_reg, address);
  383. + MV_WRITE(data_reg, val);
  384. + return;
  385. +}
  386. +
  387. +
  388. +int __init
  389. +pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  390. +{
  391. + u16 cmd;
  392. + u32 val;
  393. + int irq = 0;
  394. +
  395. + if ((dev->bus->number == 0) && (slot == 0)) {
  396. + write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
  397. + read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
  398. + printk("BAR0 at slot 0 = %x\n", val);
  399. + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
  400. + } else if((dev->bus->number == 0) && (slot == 0x1)) {
  401. + write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
  402. + read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
  403. + printk("BAR0 at slot 1 = %x\n", val);
  404. + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
  405. + } else if((dev->bus->number == 0) && (slot == 0x2)) {
  406. + write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
  407. + read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
  408. + printk("BAR0 at slot 2 = %x\n", val);
  409. + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
  410. + } else if ((dev->bus->number == 1) && (slot == 0x0)) {
  411. + switch (pcie_link_status) {
  412. + case 2:
  413. + case 6:
  414. + irq = RALINK_INT_PCIE1;
  415. + break;
  416. + case 4:
  417. + irq = RALINK_INT_PCIE2;
  418. + break;
  419. + default:
  420. + irq = RALINK_INT_PCIE0;
  421. + }
  422. + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
  423. + } else if ((dev->bus->number == 2) && (slot == 0x0)) {
  424. + switch (pcie_link_status) {
  425. + case 5:
  426. + case 6:
  427. + irq = RALINK_INT_PCIE2;
  428. + break;
  429. + default:
  430. + irq = RALINK_INT_PCIE1;
  431. + }
  432. + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
  433. + } else if ((dev->bus->number == 2) && (slot == 0x1)) {
  434. + switch (pcie_link_status) {
  435. + case 5:
  436. + case 6:
  437. + irq = RALINK_INT_PCIE2;
  438. + break;
  439. + default:
  440. + irq = RALINK_INT_PCIE1;
  441. + }
  442. + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
  443. + } else if ((dev->bus->number ==3) && (slot == 0x0)) {
  444. + irq = RALINK_INT_PCIE2;
  445. + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
  446. + } else if ((dev->bus->number ==3) && (slot == 0x1)) {
  447. + irq = RALINK_INT_PCIE2;
  448. + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
  449. + } else if ((dev->bus->number ==3) && (slot == 0x2)) {
  450. + irq = RALINK_INT_PCIE2;
  451. + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
  452. + } else {
  453. + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
  454. + return 0;
  455. + }
  456. +
  457. + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
  458. + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
  459. + pci_read_config_word(dev, PCI_COMMAND, &cmd);
  460. + cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  461. + pci_write_config_word(dev, PCI_COMMAND, cmd);
  462. + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
  463. + return irq;
  464. +}
  465. +
  466. +void
  467. +set_pcie_phy(u32 *addr, int start_b, int bits, int val)
  468. +{
  469. +// printk("0x%p:", addr);
  470. +// printk(" %x", *addr);
  471. + *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
  472. + *(unsigned int *)(addr) |= val << start_b;
  473. +// printk(" -> %x\n", *addr);
  474. +}
  475. +
  476. +void
  477. +bypass_pipe_rst(void)
  478. +{
  479. +#if defined (CONFIG_PCIE_PORT0)
  480. + /* PCIe Port 0 */
  481. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
  482. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
  483. +#endif
  484. +#if defined (CONFIG_PCIE_PORT1)
  485. + /* PCIe Port 1 */
  486. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
  487. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
  488. +#endif
  489. +#if defined (CONFIG_PCIE_PORT2)
  490. + /* PCIe Port 2 */
  491. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
  492. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
  493. +#endif
  494. +}
  495. +
  496. +void
  497. +set_phy_for_ssc(void)
  498. +{
  499. + unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
  500. +
  501. + reg = (reg >> 6) & 0x7;
  502. +#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
  503. + /* Set PCIe Port0 & Port1 PHY to disable SSC */
  504. + /* Debug Xtal Type */
  505. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
  506. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
  507. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
  508. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
  509. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
  510. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
  511. + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
  512. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
  513. + printk("***** Xtal 40MHz *****\n");
  514. + } else { // 25MHz | 20MHz Xtal
  515. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
  516. + if (reg >= 6) {
  517. + printk("***** Xtal 25MHz *****\n");
  518. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
  519. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
  520. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
  521. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
  522. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
  523. + } else {
  524. + printk("***** Xtal 20MHz *****\n");
  525. + }
  526. + }
  527. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
  528. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
  529. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
  530. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
  531. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
  532. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
  533. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
  534. + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
  535. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
  536. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
  537. + }
  538. + /* Enable PHY and disable force mode */
  539. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
  540. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
  541. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
  542. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
  543. +#endif
  544. +#if defined (CONFIG_PCIE_PORT2)
  545. + /* Set PCIe Port2 PHY to disable SSC */
  546. + /* Debug Xtal Type */
  547. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
  548. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
  549. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
  550. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
  551. + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
  552. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
  553. + } else { // 25MHz | 20MHz Xtal
  554. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
  555. + if (reg >= 6) { // 25MHz Xtal
  556. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
  557. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
  558. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
  559. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
  560. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
  561. + }
  562. + }
  563. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
  564. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
  565. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
  566. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
  567. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
  568. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
  569. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
  570. + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
  571. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
  572. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
  573. + }
  574. + /* Enable PHY and disable force mode */
  575. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
  576. + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
  577. +#endif
  578. +}
  579. +
  580. +void setup_cm_memory_region(struct resource *mem_resource)
  581. +{
  582. + resource_size_t mask;
  583. + if (mips_cm_numiocu()) {
  584. + /* FIXME: hardware doesn't accept mask values with 1s after
  585. + 0s (e.g. 0xffef), so it would be great to warn if that's
  586. + about to happen */
  587. + mask = ~(mem_resource->end - mem_resource->start);
  588. +
  589. + write_gcr_reg1_base(mem_resource->start);
  590. + write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
  591. + printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
  592. + read_gcr_reg1_base(),
  593. + read_gcr_reg1_mask());
  594. + }
  595. +}
  596. +
  597. +static int mt7621_pci_probe(struct platform_device *pdev)
  598. +{
  599. + unsigned long val = 0;
  600. +
  601. + iomem_resource.start = 0;
  602. + iomem_resource.end= ~0;
  603. + ioport_resource.start= 0;
  604. + ioport_resource.end = ~0;
  605. +
  606. +#if defined (CONFIG_PCIE_PORT0)
  607. + val = RALINK_PCIE0_RST;
  608. +#endif
  609. +#if defined (CONFIG_PCIE_PORT1)
  610. + val |= RALINK_PCIE1_RST;
  611. +#endif
  612. +#if defined (CONFIG_PCIE_PORT2)
  613. + val |= RALINK_PCIE2_RST;
  614. +#endif
  615. + ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
  616. + printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
  617. +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
  618. + *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
  619. + *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
  620. + mdelay(100);
  621. + *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
  622. + mdelay(100);
  623. + *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
  624. +
  625. + mdelay(100);
  626. +#else
  627. + *(unsigned int *)(0xbe000060) &= ~0x00000c00;
  628. +#endif
  629. +#if defined (CONFIG_PCIE_PORT0)
  630. + val = RALINK_PCIE0_RST;
  631. +#endif
  632. +#if defined (CONFIG_PCIE_PORT1)
  633. + val |= RALINK_PCIE1_RST;
  634. +#endif
  635. +#if defined (CONFIG_PCIE_PORT2)
  636. + val |= RALINK_PCIE2_RST;
  637. +#endif
  638. + DEASSERT_SYSRST_PCIE(val);
  639. + printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
  640. +
  641. + if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
  642. + bypass_pipe_rst();
  643. + set_phy_for_ssc();
  644. + printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
  645. +
  646. +#if defined (CONFIG_PCIE_PORT0)
  647. + read_config(0, 0, 0, 0x70c, &val);
  648. + printk("Port 0 N_FTS = %x\n", (unsigned int)val);
  649. +#endif
  650. +#if defined (CONFIG_PCIE_PORT1)
  651. + read_config(0, 1, 0, 0x70c, &val);
  652. + printk("Port 1 N_FTS = %x\n", (unsigned int)val);
  653. +#endif
  654. +#if defined (CONFIG_PCIE_PORT2)
  655. + read_config(0, 2, 0, 0x70c, &val);
  656. + printk("Port 2 N_FTS = %x\n", (unsigned int)val);
  657. +#endif
  658. +
  659. + RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
  660. + RALINK_SYSCFG1 &= ~(0x30);
  661. + RALINK_SYSCFG1 |= (2<<4);
  662. + RALINK_PCIE_CLK_GEN &= 0x7fffffff;
  663. + RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
  664. + RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
  665. + RALINK_PCIE_CLK_GEN |= 0x80000000;
  666. + mdelay(50);
  667. + RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
  668. +
  669. +
  670. +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
  671. + *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
  672. + mdelay(100);
  673. +#else
  674. + RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
  675. +#endif
  676. + mdelay(500);
  677. +
  678. +
  679. + mdelay(500);
  680. +#if defined (CONFIG_PCIE_PORT0)
  681. + if(( RALINK_PCI0_STATUS & 0x1) == 0)
  682. + {
  683. + printk("PCIE0 no card, disable it(RST&CLK)\n");
  684. + ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
  685. + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
  686. + pcie_link_status &= ~(1<<0);
  687. + } else {
  688. + pcie_link_status |= 1<<0;
  689. + RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
  690. + }
  691. +#endif
  692. +#if defined (CONFIG_PCIE_PORT1)
  693. + if(( RALINK_PCI1_STATUS & 0x1) == 0)
  694. + {
  695. + printk("PCIE1 no card, disable it(RST&CLK)\n");
  696. + ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
  697. + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
  698. + pcie_link_status &= ~(1<<1);
  699. + } else {
  700. + pcie_link_status |= 1<<1;
  701. + RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
  702. + }
  703. +#endif
  704. +#if defined (CONFIG_PCIE_PORT2)
  705. + if (( RALINK_PCI2_STATUS & 0x1) == 0) {
  706. + printk("PCIE2 no card, disable it(RST&CLK)\n");
  707. + ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
  708. + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
  709. + pcie_link_status &= ~(1<<2);
  710. + } else {
  711. + pcie_link_status |= 1<<2;
  712. + RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
  713. + }
  714. +#endif
  715. + if (pcie_link_status == 0)
  716. + return 0;
  717. +
  718. +/*
  719. +pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
  720. +3'b000 x x x
  721. +3'b001 x x 0
  722. +3'b010 x 0 x
  723. +3'b011 x 1 0
  724. +3'b100 0 x x
  725. +3'b101 1 x 0
  726. +3'b110 1 0 x
  727. +3'b111 2 1 0
  728. +*/
  729. + switch(pcie_link_status) {
  730. + case 2:
  731. + RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
  732. + RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
  733. + RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
  734. + break;
  735. + case 4:
  736. + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
  737. + RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
  738. + RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
  739. + RALINK_PCI_PCICFG_ADDR |= 0x0 << 24; //port2
  740. + break;
  741. + case 5:
  742. + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
  743. + RALINK_PCI_PCICFG_ADDR |= 0x0 << 16; //port0
  744. + RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
  745. + RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
  746. + break;
  747. + case 6:
  748. + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
  749. + RALINK_PCI_PCICFG_ADDR |= 0x2 << 16; //port0
  750. + RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
  751. + RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
  752. + break;
  753. + }
  754. + printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
  755. + //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
  756. +
  757. +/*
  758. + ioport_resource.start = mt7621_res_pci_io1.start;
  759. + ioport_resource.end = mt7621_res_pci_io1.end;
  760. +*/
  761. +
  762. + RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
  763. + RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
  764. +
  765. +#if defined (CONFIG_PCIE_PORT0)
  766. + //PCIe0
  767. + if((pcie_link_status & 0x1) != 0) {
  768. + RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
  769. + RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
  770. + RALINK_PCI0_CLASS = 0x06040001;
  771. + printk("PCIE0 enabled\n");
  772. + }
  773. +#endif
  774. +#if defined (CONFIG_PCIE_PORT1)
  775. + //PCIe1
  776. + if ((pcie_link_status & 0x2) != 0) {
  777. + RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
  778. + RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
  779. + RALINK_PCI1_CLASS = 0x06040001;
  780. + printk("PCIE1 enabled\n");
  781. + }
  782. +#endif
  783. +#if defined (CONFIG_PCIE_PORT2)
  784. + //PCIe2
  785. + if ((pcie_link_status & 0x4) != 0) {
  786. + RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
  787. + RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
  788. + RALINK_PCI2_CLASS = 0x06040001;
  789. + printk("PCIE2 enabled\n");
  790. + }
  791. +#endif
  792. +
  793. +
  794. + switch(pcie_link_status) {
  795. + case 7:
  796. + read_config(0, 2, 0, 0x4, &val);
  797. + write_config(0, 2, 0, 0x4, val|0x4);
  798. + // write_config(0, 1, 0, 0x4, val|0x7);
  799. + read_config(0, 2, 0, 0x70c, &val);
  800. + val &= ~(0xff)<<8;
  801. + val |= 0x50<<8;
  802. + write_config(0, 2, 0, 0x70c, val);
  803. + case 3:
  804. + case 5:
  805. + case 6:
  806. + read_config(0, 1, 0, 0x4, &val);
  807. + write_config(0, 1, 0, 0x4, val|0x4);
  808. + // write_config(0, 1, 0, 0x4, val|0x7);
  809. + read_config(0, 1, 0, 0x70c, &val);
  810. + val &= ~(0xff)<<8;
  811. + val |= 0x50<<8;
  812. + write_config(0, 1, 0, 0x70c, val);
  813. + default:
  814. + read_config(0, 0, 0, 0x4, &val);
  815. + write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
  816. + // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
  817. + read_config(0, 0, 0, 0x70c, &val);
  818. + val &= ~(0xff)<<8;
  819. + val |= 0x50<<8;
  820. + write_config(0, 0, 0, 0x70c, val);
  821. + }
  822. +
  823. + pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
  824. + setup_cm_memory_region(mt7621_controller.mem_resource);
  825. + register_pci_controller(&mt7621_controller);
  826. + return 0;
  827. +
  828. +}
  829. +
  830. +int pcibios_plat_dev_init(struct pci_dev *dev)
  831. +{
  832. + return 0;
  833. +}
  834. +
  835. +static const struct of_device_id mt7621_pci_ids[] = {
  836. + { .compatible = "mediatek,mt7621-pci" },
  837. + {},
  838. +};
  839. +MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
  840. +
  841. +static struct platform_driver mt7621_pci_driver = {
  842. + .probe = mt7621_pci_probe,
  843. + .driver = {
  844. + .name = "mt7621-pci",
  845. + .owner = THIS_MODULE,
  846. + .of_match_table = of_match_ptr(mt7621_pci_ids),
  847. + },
  848. +};
  849. +
  850. +static int __init mt7621_pci_init(void)
  851. +{
  852. + return platform_driver_register(&mt7621_pci_driver);
  853. +}
  854. +
  855. +arch_initcall(mt7621_pci_init);