0027-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch 11 KB

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  1. From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Mon, 4 Aug 2014 20:36:29 +0200
  4. Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC
  5. Add gpio driver for Ralink SoC. This driver makes the gpio core on
  6. RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
  7. Signed-off-by: John Crispin <blogic@openwrt.org>
  8. Cc: linux-mips@linux-mips.org
  9. Cc: linux-gpio@vger.kernel.org
  10. ---
  11. arch/mips/include/asm/mach-ralink/gpio.h | 24 ++
  12. drivers/gpio/Kconfig | 6 +
  13. drivers/gpio/Makefile | 1 +
  14. drivers/gpio/gpio-ralink.c | 355 ++++++++++++++++++++++++++++++
  15. 4 files changed, 386 insertions(+)
  16. create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
  17. create mode 100644 drivers/gpio/gpio-ralink.c
  18. --- /dev/null
  19. +++ b/arch/mips/include/asm/mach-ralink/gpio.h
  20. @@ -0,0 +1,24 @@
  21. +/*
  22. + * Ralink SoC GPIO API support
  23. + *
  24. + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  25. + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  26. + *
  27. + * This program is free software; you can redistribute it and/or modify it
  28. + * under the terms of the GNU General Public License version 2 as published
  29. + * by the Free Software Foundation.
  30. + *
  31. + */
  32. +
  33. +#ifndef __ASM_MACH_RALINK_GPIO_H
  34. +#define __ASM_MACH_RALINK_GPIO_H
  35. +
  36. +#define ARCH_NR_GPIOS 128
  37. +#include <asm-generic/gpio.h>
  38. +
  39. +#define gpio_get_value __gpio_get_value
  40. +#define gpio_set_value __gpio_set_value
  41. +#define gpio_cansleep __gpio_cansleep
  42. +#define gpio_to_irq __gpio_to_irq
  43. +
  44. +#endif /* __ASM_MACH_RALINK_GPIO_H */
  45. --- a/drivers/gpio/Kconfig
  46. +++ b/drivers/gpio/Kconfig
  47. @@ -352,6 +352,12 @@ config GPIO_SAMSUNG
  48. Legacy GPIO support. Use only for platforms without support for
  49. pinctrl.
  50. +config GPIO_RALINK
  51. + bool "Ralink GPIO Support"
  52. + depends on RALINK
  53. + help
  54. + Say yes here to support the Ralink SoC GPIO device
  55. +
  56. config GPIO_SPEAR_SPICS
  57. bool "ST SPEAr13xx SPI Chip Select as GPIO support"
  58. depends on PLAT_SPEAR
  59. --- a/drivers/gpio/Makefile
  60. +++ b/drivers/gpio/Makefile
  61. @@ -76,6 +76,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf85
  62. obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
  63. obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
  64. obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
  65. +obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
  66. obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
  67. obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
  68. obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
  69. --- /dev/null
  70. +++ b/drivers/gpio/gpio-ralink.c
  71. @@ -0,0 +1,355 @@
  72. +/*
  73. + * This program is free software; you can redistribute it and/or modify it
  74. + * under the terms of the GNU General Public License version 2 as published
  75. + * by the Free Software Foundation.
  76. + *
  77. + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  78. + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  79. + */
  80. +
  81. +#include <linux/module.h>
  82. +#include <linux/io.h>
  83. +#include <linux/gpio.h>
  84. +#include <linux/spinlock.h>
  85. +#include <linux/platform_device.h>
  86. +#include <linux/of_irq.h>
  87. +#include <linux/irqdomain.h>
  88. +#include <linux/interrupt.h>
  89. +
  90. +enum ralink_gpio_reg {
  91. + GPIO_REG_INT = 0,
  92. + GPIO_REG_EDGE,
  93. + GPIO_REG_RENA,
  94. + GPIO_REG_FENA,
  95. + GPIO_REG_DATA,
  96. + GPIO_REG_DIR,
  97. + GPIO_REG_POL,
  98. + GPIO_REG_SET,
  99. + GPIO_REG_RESET,
  100. + GPIO_REG_TOGGLE,
  101. + GPIO_REG_MAX
  102. +};
  103. +
  104. +struct ralink_gpio_chip {
  105. + struct gpio_chip chip;
  106. + u8 regs[GPIO_REG_MAX];
  107. +
  108. + spinlock_t lock;
  109. + void __iomem *membase;
  110. + struct irq_domain *domain;
  111. + int irq;
  112. +
  113. + u32 rising;
  114. + u32 falling;
  115. +};
  116. +
  117. +#define MAP_MAX 4
  118. +static struct irq_domain *irq_map[MAP_MAX];
  119. +static int irq_map_count;
  120. +static atomic_t irq_refcount = ATOMIC_INIT(0);
  121. +
  122. +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
  123. +{
  124. + struct ralink_gpio_chip *rg;
  125. +
  126. + rg = container_of(chip, struct ralink_gpio_chip, chip);
  127. +
  128. + return rg;
  129. +}
  130. +
  131. +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
  132. +{
  133. + iowrite32(val, rg->membase + rg->regs[reg]);
  134. +}
  135. +
  136. +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
  137. +{
  138. + return ioread32(rg->membase + rg->regs[reg]);
  139. +}
  140. +
  141. +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  142. +{
  143. + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
  144. +
  145. + rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
  146. +}
  147. +
  148. +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
  149. +{
  150. + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
  151. +
  152. + return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
  153. +}
  154. +
  155. +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  156. +{
  157. + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
  158. + unsigned long flags;
  159. + u32 t;
  160. +
  161. + spin_lock_irqsave(&rg->lock, flags);
  162. + t = rt_gpio_r32(rg, GPIO_REG_DIR);
  163. + t &= ~BIT(offset);
  164. + rt_gpio_w32(rg, GPIO_REG_DIR, t);
  165. + spin_unlock_irqrestore(&rg->lock, flags);
  166. +
  167. + return 0;
  168. +}
  169. +
  170. +static int ralink_gpio_direction_output(struct gpio_chip *chip,
  171. + unsigned offset, int value)
  172. +{
  173. + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
  174. + unsigned long flags;
  175. + u32 t;
  176. +
  177. + spin_lock_irqsave(&rg->lock, flags);
  178. + ralink_gpio_set(chip, offset, value);
  179. + t = rt_gpio_r32(rg, GPIO_REG_DIR);
  180. + t |= BIT(offset);
  181. + rt_gpio_w32(rg, GPIO_REG_DIR, t);
  182. + spin_unlock_irqrestore(&rg->lock, flags);
  183. +
  184. + return 0;
  185. +}
  186. +
  187. +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
  188. +{
  189. + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
  190. +
  191. + if (rg->irq < 1)
  192. + return -1;
  193. +
  194. + return irq_create_mapping(rg->domain, pin);
  195. +}
  196. +
  197. +static void ralink_gpio_irq_handler(struct irq_desc *desc)
  198. +{
  199. + int i;
  200. +
  201. + for (i = 0; i < irq_map_count; i++) {
  202. + struct irq_domain *domain = irq_map[i];
  203. + struct ralink_gpio_chip *rg;
  204. + unsigned long pending;
  205. + int bit;
  206. +
  207. + rg = (struct ralink_gpio_chip *) domain->host_data;
  208. + pending = rt_gpio_r32(rg, GPIO_REG_INT);
  209. +
  210. + for_each_set_bit(bit, &pending, rg->chip.ngpio) {
  211. + u32 map = irq_find_mapping(domain, bit);
  212. + generic_handle_irq(map);
  213. + rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
  214. + }
  215. + }
  216. +}
  217. +
  218. +static void ralink_gpio_irq_unmask(struct irq_data *d)
  219. +{
  220. + struct ralink_gpio_chip *rg;
  221. + unsigned long flags;
  222. + u32 rise, fall;
  223. +
  224. + rg = (struct ralink_gpio_chip *) d->domain->host_data;
  225. + rise = rt_gpio_r32(rg, GPIO_REG_RENA);
  226. + fall = rt_gpio_r32(rg, GPIO_REG_FENA);
  227. +
  228. + spin_lock_irqsave(&rg->lock, flags);
  229. + rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));
  230. + rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));
  231. + spin_unlock_irqrestore(&rg->lock, flags);
  232. +}
  233. +
  234. +static void ralink_gpio_irq_mask(struct irq_data *d)
  235. +{
  236. + struct ralink_gpio_chip *rg;
  237. + unsigned long flags;
  238. + u32 rise, fall;
  239. +
  240. + rg = (struct ralink_gpio_chip *) d->domain->host_data;
  241. + rise = rt_gpio_r32(rg, GPIO_REG_RENA);
  242. + fall = rt_gpio_r32(rg, GPIO_REG_FENA);
  243. +
  244. + spin_lock_irqsave(&rg->lock, flags);
  245. + rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));
  246. + rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));
  247. + spin_unlock_irqrestore(&rg->lock, flags);
  248. +}
  249. +
  250. +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
  251. +{
  252. + struct ralink_gpio_chip *rg;
  253. + u32 mask = BIT(d->hwirq);
  254. +
  255. + rg = (struct ralink_gpio_chip *) d->domain->host_data;
  256. +
  257. + if (type == IRQ_TYPE_PROBE) {
  258. + if ((rg->rising | rg->falling) & mask)
  259. + return 0;
  260. +
  261. + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  262. + }
  263. +
  264. + if (type & IRQ_TYPE_EDGE_RISING)
  265. + rg->rising |= mask;
  266. + else
  267. + rg->rising &= ~mask;
  268. +
  269. + if (type & IRQ_TYPE_EDGE_FALLING)
  270. + rg->falling |= mask;
  271. + else
  272. + rg->falling &= ~mask;
  273. +
  274. + return 0;
  275. +}
  276. +
  277. +static struct irq_chip ralink_gpio_irq_chip = {
  278. + .name = "GPIO",
  279. + .irq_unmask = ralink_gpio_irq_unmask,
  280. + .irq_mask = ralink_gpio_irq_mask,
  281. + .irq_mask_ack = ralink_gpio_irq_mask,
  282. + .irq_set_type = ralink_gpio_irq_type,
  283. +};
  284. +
  285. +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
  286. +{
  287. + irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
  288. + irq_set_handler_data(irq, d);
  289. +
  290. + return 0;
  291. +}
  292. +
  293. +static const struct irq_domain_ops irq_domain_ops = {
  294. + .xlate = irq_domain_xlate_onecell,
  295. + .map = gpio_map,
  296. +};
  297. +
  298. +static void ralink_gpio_irq_init(struct device_node *np,
  299. + struct ralink_gpio_chip *rg)
  300. +{
  301. + if (irq_map_count >= MAP_MAX)
  302. + return;
  303. +
  304. + rg->irq = irq_of_parse_and_map(np, 0);
  305. + if (!rg->irq)
  306. + return;
  307. +
  308. + rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
  309. + &irq_domain_ops, rg);
  310. + if (!rg->domain) {
  311. + dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
  312. + return;
  313. + }
  314. +
  315. + irq_map[irq_map_count++] = rg->domain;
  316. +
  317. + rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
  318. + rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
  319. +
  320. + if (!atomic_read(&irq_refcount))
  321. + irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
  322. + atomic_inc(&irq_refcount);
  323. +
  324. + dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
  325. +}
  326. +
  327. +static int ralink_gpio_request(struct gpio_chip *chip, unsigned offset)
  328. +{
  329. + int gpio = chip->base + offset;
  330. +
  331. + return pinctrl_request_gpio(gpio);
  332. +}
  333. +
  334. +static void ralink_gpio_free(struct gpio_chip *chip, unsigned offset)
  335. +{
  336. + int gpio = chip->base + offset;
  337. +
  338. + pinctrl_free_gpio(gpio);
  339. +}
  340. +
  341. +static int ralink_gpio_probe(struct platform_device *pdev)
  342. +{
  343. + struct device_node *np = pdev->dev.of_node;
  344. + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  345. + struct ralink_gpio_chip *rg;
  346. + const __be32 *ngpio, *gpiobase;
  347. +
  348. + if (!res) {
  349. + dev_err(&pdev->dev, "failed to find resource\n");
  350. + return -ENOMEM;
  351. + }
  352. +
  353. + rg = devm_kzalloc(&pdev->dev,
  354. + sizeof(struct ralink_gpio_chip), GFP_KERNEL);
  355. + if (!rg)
  356. + return -ENOMEM;
  357. +
  358. + rg->membase = devm_ioremap_resource(&pdev->dev, res);
  359. + if (!rg->membase) {
  360. + dev_err(&pdev->dev, "cannot remap I/O memory region\n");
  361. + return -ENOMEM;
  362. + }
  363. +
  364. + if (of_property_read_u8_array(np, "ralink,register-map",
  365. + rg->regs, GPIO_REG_MAX)) {
  366. + dev_err(&pdev->dev, "failed to read register definition\n");
  367. + return -EINVAL;
  368. + }
  369. +
  370. + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
  371. + if (!ngpio) {
  372. + dev_err(&pdev->dev, "failed to read number of pins\n");
  373. + return -EINVAL;
  374. + }
  375. +
  376. + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
  377. + if (gpiobase)
  378. + rg->chip.base = be32_to_cpu(*gpiobase);
  379. + else
  380. + rg->chip.base = -1;
  381. +
  382. + spin_lock_init(&rg->lock);
  383. +
  384. + rg->chip.dev = &pdev->dev;
  385. + rg->chip.label = dev_name(&pdev->dev);
  386. + rg->chip.of_node = np;
  387. + rg->chip.ngpio = be32_to_cpu(*ngpio);
  388. + rg->chip.direction_input = ralink_gpio_direction_input;
  389. + rg->chip.direction_output = ralink_gpio_direction_output;
  390. + rg->chip.get = ralink_gpio_get;
  391. + rg->chip.set = ralink_gpio_set;
  392. + rg->chip.request = ralink_gpio_request;
  393. + rg->chip.to_irq = ralink_gpio_to_irq;
  394. + rg->chip.free = ralink_gpio_free;
  395. +
  396. + /* set polarity to low for all lines */
  397. + rt_gpio_w32(rg, GPIO_REG_POL, 0);
  398. +
  399. + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
  400. +
  401. + ralink_gpio_irq_init(np, rg);
  402. +
  403. + return gpiochip_add(&rg->chip);
  404. +}
  405. +
  406. +static const struct of_device_id ralink_gpio_match[] = {
  407. + { .compatible = "ralink,rt2880-gpio" },
  408. + {},
  409. +};
  410. +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
  411. +
  412. +static struct platform_driver ralink_gpio_driver = {
  413. + .probe = ralink_gpio_probe,
  414. + .driver = {
  415. + .name = "rt2880_gpio",
  416. + .owner = THIS_MODULE,
  417. + .of_match_table = ralink_gpio_match,
  418. + },
  419. +};
  420. +
  421. +static int __init ralink_gpio_init(void)
  422. +{
  423. + return platform_driver_register(&ralink_gpio_driver);
  424. +}
  425. +
  426. +subsys_initcall(ralink_gpio_init);