1
0

0033-xhci-mediatek-support-MTK-xHCI-host-controller.patch 41 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517
  1. From: Chunfeng Yun <chunfeng.yun@mediatek.com>
  2. Date: Tue, 24 Nov 2015 13:09:55 +0200
  3. Subject: [PATCH] xhci: mediatek: support MTK xHCI host controller
  4. There some vendor quirks for MTK xhci host controller:
  5. 1. It defines some extra SW scheduling parameters for HW
  6. to minimize the scheduling effort for synchronous and
  7. interrupt endpoints. The parameters are put into reseved
  8. DWs of slot context and endpoint context.
  9. 2. Its IMODI unit for Interrupter Moderation register is
  10. 8 times as much as that defined in xHCI spec.
  11. 3. Its TDS in Normal TRB defines a number of packets that
  12. remains to be transferred for a TD after processing all
  13. Max packets in all previous TRBs.
  14. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
  15. Tested-by: Daniel Thompson <daniel.thompson@linaro.org>
  16. Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  17. Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
  18. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  19. ---
  20. create mode 100644 drivers/usb/host/xhci-mtk-sch.c
  21. create mode 100644 drivers/usb/host/xhci-mtk.c
  22. create mode 100644 drivers/usb/host/xhci-mtk.h
  23. --- a/drivers/usb/host/Kconfig
  24. +++ b/drivers/usb/host/Kconfig
  25. @@ -41,6 +41,15 @@ config USB_XHCI_PLATFORM
  26. If unsure, say N.
  27. +config USB_XHCI_MTK
  28. + tristate "xHCI support for Mediatek MT65xx"
  29. + select MFD_SYSCON
  30. + depends on ARCH_MEDIATEK || COMPILE_TEST
  31. + ---help---
  32. + Say 'Y' to enable the support for the xHCI host controller
  33. + found in Mediatek MT65xx SoCs.
  34. + If unsure, say N.
  35. +
  36. config USB_XHCI_MVEBU
  37. tristate "xHCI support for Marvell Armada 375/38x"
  38. select USB_XHCI_PLATFORM
  39. --- a/drivers/usb/host/Makefile
  40. +++ b/drivers/usb/host/Makefile
  41. @@ -13,6 +13,9 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
  42. xhci-hcd-y := xhci.o xhci-mem.o
  43. xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
  44. xhci-hcd-y += xhci-trace.o
  45. +ifneq ($(CONFIG_USB_XHCI_MTK), )
  46. + xhci-hcd-y += xhci-mtk-sch.o
  47. +endif
  48. xhci-plat-hcd-y := xhci-plat.o
  49. ifneq ($(CONFIG_USB_XHCI_MVEBU), )
  50. @@ -64,6 +67,7 @@ obj-$(CONFIG_USB_FHCI_HCD) += fhci.o
  51. obj-$(CONFIG_USB_XHCI_HCD) += xhci-hcd.o
  52. obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
  53. obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
  54. +obj-$(CONFIG_USB_XHCI_MTK) += xhci-mtk.o
  55. obj-$(CONFIG_USB_SL811_HCD) += sl811-hcd.o
  56. obj-$(CONFIG_USB_SL811_CS) += sl811_cs.o
  57. obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o
  58. --- /dev/null
  59. +++ b/drivers/usb/host/xhci-mtk-sch.c
  60. @@ -0,0 +1,415 @@
  61. +/*
  62. + * Copyright (c) 2015 MediaTek Inc.
  63. + * Author:
  64. + * Zhigang.Wei <zhigang.wei@mediatek.com>
  65. + * Chunfeng.Yun <chunfeng.yun@mediatek.com>
  66. + *
  67. + * This software is licensed under the terms of the GNU General Public
  68. + * License version 2, as published by the Free Software Foundation, and
  69. + * may be copied, distributed, and modified under those terms.
  70. + *
  71. + * This program is distributed in the hope that it will be useful,
  72. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  73. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  74. + * GNU General Public License for more details.
  75. + *
  76. + */
  77. +
  78. +#include <linux/kernel.h>
  79. +#include <linux/module.h>
  80. +#include <linux/slab.h>
  81. +
  82. +#include "xhci.h"
  83. +#include "xhci-mtk.h"
  84. +
  85. +#define SS_BW_BOUNDARY 51000
  86. +/* table 5-5. High-speed Isoc Transaction Limits in usb_20 spec */
  87. +#define HS_BW_BOUNDARY 6144
  88. +/* usb2 spec section11.18.1: at most 188 FS bytes per microframe */
  89. +#define FS_PAYLOAD_MAX 188
  90. +
  91. +/* mtk scheduler bitmasks */
  92. +#define EP_BPKTS(p) ((p) & 0x3f)
  93. +#define EP_BCSCOUNT(p) (((p) & 0x7) << 8)
  94. +#define EP_BBM(p) ((p) << 11)
  95. +#define EP_BOFFSET(p) ((p) & 0x3fff)
  96. +#define EP_BREPEAT(p) (((p) & 0x7fff) << 16)
  97. +
  98. +static int is_fs_or_ls(enum usb_device_speed speed)
  99. +{
  100. + return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
  101. +}
  102. +
  103. +/*
  104. +* get the index of bandwidth domains array which @ep belongs to.
  105. +*
  106. +* the bandwidth domain array is saved to @sch_array of struct xhci_hcd_mtk,
  107. +* each HS root port is treated as a single bandwidth domain,
  108. +* but each SS root port is treated as two bandwidth domains, one for IN eps,
  109. +* one for OUT eps.
  110. +* @real_port value is defined as follow according to xHCI spec:
  111. +* 1 for SSport0, ..., N+1 for SSportN, N+2 for HSport0, N+3 for HSport1, etc
  112. +* so the bandwidth domain array is organized as follow for simplification:
  113. +* SSport0-OUT, SSport0-IN, ..., SSportX-OUT, SSportX-IN, HSport0, ..., HSportY
  114. +*/
  115. +static int get_bw_index(struct xhci_hcd *xhci, struct usb_device *udev,
  116. + struct usb_host_endpoint *ep)
  117. +{
  118. + struct xhci_virt_device *virt_dev;
  119. + int bw_index;
  120. +
  121. + virt_dev = xhci->devs[udev->slot_id];
  122. +
  123. + if (udev->speed == USB_SPEED_SUPER) {
  124. + if (usb_endpoint_dir_out(&ep->desc))
  125. + bw_index = (virt_dev->real_port - 1) * 2;
  126. + else
  127. + bw_index = (virt_dev->real_port - 1) * 2 + 1;
  128. + } else {
  129. + /* add one more for each SS port */
  130. + bw_index = virt_dev->real_port + xhci->num_usb3_ports - 1;
  131. + }
  132. +
  133. + return bw_index;
  134. +}
  135. +
  136. +static void setup_sch_info(struct usb_device *udev,
  137. + struct xhci_ep_ctx *ep_ctx, struct mu3h_sch_ep_info *sch_ep)
  138. +{
  139. + u32 ep_type;
  140. + u32 ep_interval;
  141. + u32 max_packet_size;
  142. + u32 max_burst;
  143. + u32 mult;
  144. + u32 esit_pkts;
  145. +
  146. + ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
  147. + ep_interval = CTX_TO_EP_INTERVAL(le32_to_cpu(ep_ctx->ep_info));
  148. + max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
  149. + max_burst = CTX_TO_MAX_BURST(le32_to_cpu(ep_ctx->ep_info2));
  150. + mult = CTX_TO_EP_MULT(le32_to_cpu(ep_ctx->ep_info));
  151. +
  152. + sch_ep->esit = 1 << ep_interval;
  153. + sch_ep->offset = 0;
  154. + sch_ep->burst_mode = 0;
  155. +
  156. + if (udev->speed == USB_SPEED_HIGH) {
  157. + sch_ep->cs_count = 0;
  158. +
  159. + /*
  160. + * usb_20 spec section5.9
  161. + * a single microframe is enough for HS synchromous endpoints
  162. + * in a interval
  163. + */
  164. + sch_ep->num_budget_microframes = 1;
  165. + sch_ep->repeat = 0;
  166. +
  167. + /*
  168. + * xHCI spec section6.2.3.4
  169. + * @max_burst is the number of additional transactions
  170. + * opportunities per microframe
  171. + */
  172. + sch_ep->pkts = max_burst + 1;
  173. + sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
  174. + } else if (udev->speed == USB_SPEED_SUPER) {
  175. + /* usb3_r1 spec section4.4.7 & 4.4.8 */
  176. + sch_ep->cs_count = 0;
  177. + esit_pkts = (mult + 1) * (max_burst + 1);
  178. + if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
  179. + sch_ep->pkts = esit_pkts;
  180. + sch_ep->num_budget_microframes = 1;
  181. + sch_ep->repeat = 0;
  182. + }
  183. +
  184. + if (ep_type == ISOC_IN_EP || ep_type == ISOC_OUT_EP) {
  185. + if (esit_pkts <= sch_ep->esit)
  186. + sch_ep->pkts = 1;
  187. + else
  188. + sch_ep->pkts = roundup_pow_of_two(esit_pkts)
  189. + / sch_ep->esit;
  190. +
  191. + sch_ep->num_budget_microframes =
  192. + DIV_ROUND_UP(esit_pkts, sch_ep->pkts);
  193. +
  194. + if (sch_ep->num_budget_microframes > 1)
  195. + sch_ep->repeat = 1;
  196. + else
  197. + sch_ep->repeat = 0;
  198. + }
  199. + sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
  200. + } else if (is_fs_or_ls(udev->speed)) {
  201. +
  202. + /*
  203. + * usb_20 spec section11.18.4
  204. + * assume worst cases
  205. + */
  206. + sch_ep->repeat = 0;
  207. + sch_ep->pkts = 1; /* at most one packet for each microframe */
  208. + if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
  209. + sch_ep->cs_count = 3; /* at most need 3 CS*/
  210. + /* one for SS and one for budgeted transaction */
  211. + sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
  212. + sch_ep->bw_cost_per_microframe = max_packet_size;
  213. + }
  214. + if (ep_type == ISOC_OUT_EP) {
  215. +
  216. + /*
  217. + * the best case FS budget assumes that 188 FS bytes
  218. + * occur in each microframe
  219. + */
  220. + sch_ep->num_budget_microframes = DIV_ROUND_UP(
  221. + max_packet_size, FS_PAYLOAD_MAX);
  222. + sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
  223. + sch_ep->cs_count = sch_ep->num_budget_microframes;
  224. + }
  225. + if (ep_type == ISOC_IN_EP) {
  226. + /* at most need additional two CS. */
  227. + sch_ep->cs_count = DIV_ROUND_UP(
  228. + max_packet_size, FS_PAYLOAD_MAX) + 2;
  229. + sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
  230. + sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
  231. + }
  232. + }
  233. +}
  234. +
  235. +/* Get maximum bandwidth when we schedule at offset slot. */
  236. +static u32 get_max_bw(struct mu3h_sch_bw_info *sch_bw,
  237. + struct mu3h_sch_ep_info *sch_ep, u32 offset)
  238. +{
  239. + u32 num_esit;
  240. + u32 max_bw = 0;
  241. + int i;
  242. + int j;
  243. +
  244. + num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
  245. + for (i = 0; i < num_esit; i++) {
  246. + u32 base = offset + i * sch_ep->esit;
  247. +
  248. + for (j = 0; j < sch_ep->num_budget_microframes; j++) {
  249. + if (sch_bw->bus_bw[base + j] > max_bw)
  250. + max_bw = sch_bw->bus_bw[base + j];
  251. + }
  252. + }
  253. + return max_bw;
  254. +}
  255. +
  256. +static void update_bus_bw(struct mu3h_sch_bw_info *sch_bw,
  257. + struct mu3h_sch_ep_info *sch_ep, int bw_cost)
  258. +{
  259. + u32 num_esit;
  260. + u32 base;
  261. + int i;
  262. + int j;
  263. +
  264. + num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
  265. + for (i = 0; i < num_esit; i++) {
  266. + base = sch_ep->offset + i * sch_ep->esit;
  267. + for (j = 0; j < sch_ep->num_budget_microframes; j++)
  268. + sch_bw->bus_bw[base + j] += bw_cost;
  269. + }
  270. +}
  271. +
  272. +static int check_sch_bw(struct usb_device *udev,
  273. + struct mu3h_sch_bw_info *sch_bw, struct mu3h_sch_ep_info *sch_ep)
  274. +{
  275. + u32 offset;
  276. + u32 esit;
  277. + u32 num_budget_microframes;
  278. + u32 min_bw;
  279. + u32 min_index;
  280. + u32 worst_bw;
  281. + u32 bw_boundary;
  282. +
  283. + if (sch_ep->esit > XHCI_MTK_MAX_ESIT)
  284. + sch_ep->esit = XHCI_MTK_MAX_ESIT;
  285. +
  286. + esit = sch_ep->esit;
  287. + num_budget_microframes = sch_ep->num_budget_microframes;
  288. +
  289. + /*
  290. + * Search through all possible schedule microframes.
  291. + * and find a microframe where its worst bandwidth is minimum.
  292. + */
  293. + min_bw = ~0;
  294. + min_index = 0;
  295. + for (offset = 0; offset < esit; offset++) {
  296. + if ((offset + num_budget_microframes) > sch_ep->esit)
  297. + break;
  298. +
  299. + /*
  300. + * usb_20 spec section11.18:
  301. + * must never schedule Start-Split in Y6
  302. + */
  303. + if (is_fs_or_ls(udev->speed) && (offset % 8 == 6))
  304. + continue;
  305. +
  306. + worst_bw = get_max_bw(sch_bw, sch_ep, offset);
  307. + if (min_bw > worst_bw) {
  308. + min_bw = worst_bw;
  309. + min_index = offset;
  310. + }
  311. + if (min_bw == 0)
  312. + break;
  313. + }
  314. + sch_ep->offset = min_index;
  315. +
  316. + bw_boundary = (udev->speed == USB_SPEED_SUPER)
  317. + ? SS_BW_BOUNDARY : HS_BW_BOUNDARY;
  318. +
  319. + /* check bandwidth */
  320. + if (min_bw + sch_ep->bw_cost_per_microframe > bw_boundary)
  321. + return -ERANGE;
  322. +
  323. + /* update bus bandwidth info */
  324. + update_bus_bw(sch_bw, sch_ep, sch_ep->bw_cost_per_microframe);
  325. +
  326. + return 0;
  327. +}
  328. +
  329. +static bool need_bw_sch(struct usb_host_endpoint *ep,
  330. + enum usb_device_speed speed, int has_tt)
  331. +{
  332. + /* only for periodic endpoints */
  333. + if (usb_endpoint_xfer_control(&ep->desc)
  334. + || usb_endpoint_xfer_bulk(&ep->desc))
  335. + return false;
  336. +
  337. + /*
  338. + * for LS & FS periodic endpoints which its device don't attach
  339. + * to TT are also ignored, root-hub will schedule them directly
  340. + */
  341. + if (is_fs_or_ls(speed) && !has_tt)
  342. + return false;
  343. +
  344. + return true;
  345. +}
  346. +
  347. +int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk)
  348. +{
  349. + struct mu3h_sch_bw_info *sch_array;
  350. + int num_usb_bus;
  351. + int i;
  352. +
  353. + /* ss IN and OUT are separated */
  354. + num_usb_bus = mtk->num_u3_ports * 2 + mtk->num_u2_ports;
  355. +
  356. + sch_array = kcalloc(num_usb_bus, sizeof(*sch_array), GFP_KERNEL);
  357. + if (sch_array == NULL)
  358. + return -ENOMEM;
  359. +
  360. + for (i = 0; i < num_usb_bus; i++)
  361. + INIT_LIST_HEAD(&sch_array[i].bw_ep_list);
  362. +
  363. + mtk->sch_array = sch_array;
  364. +
  365. + return 0;
  366. +}
  367. +EXPORT_SYMBOL_GPL(xhci_mtk_sch_init);
  368. +
  369. +void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk)
  370. +{
  371. + kfree(mtk->sch_array);
  372. +}
  373. +EXPORT_SYMBOL_GPL(xhci_mtk_sch_exit);
  374. +
  375. +int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
  376. + struct usb_host_endpoint *ep)
  377. +{
  378. + struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
  379. + struct xhci_hcd *xhci;
  380. + struct xhci_ep_ctx *ep_ctx;
  381. + struct xhci_slot_ctx *slot_ctx;
  382. + struct xhci_virt_device *virt_dev;
  383. + struct mu3h_sch_bw_info *sch_bw;
  384. + struct mu3h_sch_ep_info *sch_ep;
  385. + struct mu3h_sch_bw_info *sch_array;
  386. + unsigned int ep_index;
  387. + int bw_index;
  388. + int ret = 0;
  389. +
  390. + xhci = hcd_to_xhci(hcd);
  391. + virt_dev = xhci->devs[udev->slot_id];
  392. + ep_index = xhci_get_endpoint_index(&ep->desc);
  393. + slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  394. + ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
  395. + sch_array = mtk->sch_array;
  396. +
  397. + xhci_dbg(xhci, "%s() type:%d, speed:%d, mpkt:%d, dir:%d, ep:%p\n",
  398. + __func__, usb_endpoint_type(&ep->desc), udev->speed,
  399. + GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)),
  400. + usb_endpoint_dir_in(&ep->desc), ep);
  401. +
  402. + if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
  403. + return 0;
  404. +
  405. + bw_index = get_bw_index(xhci, udev, ep);
  406. + sch_bw = &sch_array[bw_index];
  407. +
  408. + sch_ep = kzalloc(sizeof(struct mu3h_sch_ep_info), GFP_NOIO);
  409. + if (!sch_ep)
  410. + return -ENOMEM;
  411. +
  412. + setup_sch_info(udev, ep_ctx, sch_ep);
  413. +
  414. + ret = check_sch_bw(udev, sch_bw, sch_ep);
  415. + if (ret) {
  416. + xhci_err(xhci, "Not enough bandwidth!\n");
  417. + kfree(sch_ep);
  418. + return -ENOSPC;
  419. + }
  420. +
  421. + list_add_tail(&sch_ep->endpoint, &sch_bw->bw_ep_list);
  422. + sch_ep->ep = ep;
  423. +
  424. + ep_ctx->reserved[0] |= cpu_to_le32(EP_BPKTS(sch_ep->pkts)
  425. + | EP_BCSCOUNT(sch_ep->cs_count) | EP_BBM(sch_ep->burst_mode));
  426. + ep_ctx->reserved[1] |= cpu_to_le32(EP_BOFFSET(sch_ep->offset)
  427. + | EP_BREPEAT(sch_ep->repeat));
  428. +
  429. + xhci_dbg(xhci, " PKTS:%x, CSCOUNT:%x, BM:%x, OFFSET:%x, REPEAT:%x\n",
  430. + sch_ep->pkts, sch_ep->cs_count, sch_ep->burst_mode,
  431. + sch_ep->offset, sch_ep->repeat);
  432. +
  433. + return 0;
  434. +}
  435. +EXPORT_SYMBOL_GPL(xhci_mtk_add_ep_quirk);
  436. +
  437. +void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
  438. + struct usb_host_endpoint *ep)
  439. +{
  440. + struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
  441. + struct xhci_hcd *xhci;
  442. + struct xhci_slot_ctx *slot_ctx;
  443. + struct xhci_virt_device *virt_dev;
  444. + struct mu3h_sch_bw_info *sch_array;
  445. + struct mu3h_sch_bw_info *sch_bw;
  446. + struct mu3h_sch_ep_info *sch_ep;
  447. + int bw_index;
  448. +
  449. + xhci = hcd_to_xhci(hcd);
  450. + virt_dev = xhci->devs[udev->slot_id];
  451. + slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
  452. + sch_array = mtk->sch_array;
  453. +
  454. + xhci_dbg(xhci, "%s() type:%d, speed:%d, mpks:%d, dir:%d, ep:%p\n",
  455. + __func__, usb_endpoint_type(&ep->desc), udev->speed,
  456. + GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)),
  457. + usb_endpoint_dir_in(&ep->desc), ep);
  458. +
  459. + if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
  460. + return;
  461. +
  462. + bw_index = get_bw_index(xhci, udev, ep);
  463. + sch_bw = &sch_array[bw_index];
  464. +
  465. + list_for_each_entry(sch_ep, &sch_bw->bw_ep_list, endpoint) {
  466. + if (sch_ep->ep == ep) {
  467. + update_bus_bw(sch_bw, sch_ep,
  468. + -sch_ep->bw_cost_per_microframe);
  469. + list_del(&sch_ep->endpoint);
  470. + kfree(sch_ep);
  471. + break;
  472. + }
  473. + }
  474. +}
  475. +EXPORT_SYMBOL_GPL(xhci_mtk_drop_ep_quirk);
  476. --- /dev/null
  477. +++ b/drivers/usb/host/xhci-mtk.c
  478. @@ -0,0 +1,763 @@
  479. +/*
  480. + * MediaTek xHCI Host Controller Driver
  481. + *
  482. + * Copyright (c) 2015 MediaTek Inc.
  483. + * Author:
  484. + * Chunfeng Yun <chunfeng.yun@mediatek.com>
  485. + *
  486. + * This software is licensed under the terms of the GNU General Public
  487. + * License version 2, as published by the Free Software Foundation, and
  488. + * may be copied, distributed, and modified under those terms.
  489. + *
  490. + * This program is distributed in the hope that it will be useful,
  491. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  492. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  493. + * GNU General Public License for more details.
  494. + *
  495. + */
  496. +
  497. +#include <linux/clk.h>
  498. +#include <linux/dma-mapping.h>
  499. +#include <linux/iopoll.h>
  500. +#include <linux/kernel.h>
  501. +#include <linux/mfd/syscon.h>
  502. +#include <linux/module.h>
  503. +#include <linux/of.h>
  504. +#include <linux/phy/phy.h>
  505. +#include <linux/platform_device.h>
  506. +#include <linux/pm_runtime.h>
  507. +#include <linux/regmap.h>
  508. +#include <linux/regulator/consumer.h>
  509. +
  510. +#include "xhci.h"
  511. +#include "xhci-mtk.h"
  512. +
  513. +/* ip_pw_ctrl0 register */
  514. +#define CTRL0_IP_SW_RST BIT(0)
  515. +
  516. +/* ip_pw_ctrl1 register */
  517. +#define CTRL1_IP_HOST_PDN BIT(0)
  518. +
  519. +/* ip_pw_ctrl2 register */
  520. +#define CTRL2_IP_DEV_PDN BIT(0)
  521. +
  522. +/* ip_pw_sts1 register */
  523. +#define STS1_IP_SLEEP_STS BIT(30)
  524. +#define STS1_XHCI_RST BIT(11)
  525. +#define STS1_SYS125_RST BIT(10)
  526. +#define STS1_REF_RST BIT(8)
  527. +#define STS1_SYSPLL_STABLE BIT(0)
  528. +
  529. +/* ip_xhci_cap register */
  530. +#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
  531. +#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
  532. +
  533. +/* u3_ctrl_p register */
  534. +#define CTRL_U3_PORT_HOST_SEL BIT(2)
  535. +#define CTRL_U3_PORT_PDN BIT(1)
  536. +#define CTRL_U3_PORT_DIS BIT(0)
  537. +
  538. +/* u2_ctrl_p register */
  539. +#define CTRL_U2_PORT_HOST_SEL BIT(2)
  540. +#define CTRL_U2_PORT_PDN BIT(1)
  541. +#define CTRL_U2_PORT_DIS BIT(0)
  542. +
  543. +/* u2_phy_pll register */
  544. +#define CTRL_U2_FORCE_PLL_STB BIT(28)
  545. +
  546. +#define PERI_WK_CTRL0 0x400
  547. +#define UWK_CTR0_0P_LS_PE BIT(8) /* posedge */
  548. +#define UWK_CTR0_0P_LS_NE BIT(7) /* negedge for 0p linestate*/
  549. +#define UWK_CTL1_1P_LS_C(x) (((x) & 0xf) << 1)
  550. +#define UWK_CTL1_1P_LS_E BIT(0)
  551. +
  552. +#define PERI_WK_CTRL1 0x404
  553. +#define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26)
  554. +#define UWK_CTL1_IS_E BIT(25)
  555. +#define UWK_CTL1_0P_LS_C(x) (((x) & 0xf) << 21)
  556. +#define UWK_CTL1_0P_LS_E BIT(20)
  557. +#define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */
  558. +#define UWK_CTL1_IDDIG_E BIT(10) /* enable debounce */
  559. +#define UWK_CTL1_IDDIG_P BIT(9) /* polarity */
  560. +#define UWK_CTL1_0P_LS_P BIT(7)
  561. +#define UWK_CTL1_IS_P BIT(6) /* polarity for ip sleep */
  562. +
  563. +enum ssusb_wakeup_src {
  564. + SSUSB_WK_IP_SLEEP = 1,
  565. + SSUSB_WK_LINE_STATE = 2,
  566. +};
  567. +
  568. +static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
  569. +{
  570. + struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
  571. + u32 value, check_val;
  572. + int ret;
  573. + int i;
  574. +
  575. + /* power on host ip */
  576. + value = readl(&ippc->ip_pw_ctr1);
  577. + value &= ~CTRL1_IP_HOST_PDN;
  578. + writel(value, &ippc->ip_pw_ctr1);
  579. +
  580. + /* power on and enable all u3 ports */
  581. + for (i = 0; i < mtk->num_u3_ports; i++) {
  582. + value = readl(&ippc->u3_ctrl_p[i]);
  583. + value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
  584. + value |= CTRL_U3_PORT_HOST_SEL;
  585. + writel(value, &ippc->u3_ctrl_p[i]);
  586. + }
  587. +
  588. + /* power on and enable all u2 ports */
  589. + for (i = 0; i < mtk->num_u2_ports; i++) {
  590. + value = readl(&ippc->u2_ctrl_p[i]);
  591. + value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
  592. + value |= CTRL_U2_PORT_HOST_SEL;
  593. + writel(value, &ippc->u2_ctrl_p[i]);
  594. + }
  595. +
  596. + /*
  597. + * wait for clocks to be stable, and clock domains reset to
  598. + * be inactive after power on and enable ports
  599. + */
  600. + check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
  601. + STS1_SYS125_RST | STS1_XHCI_RST;
  602. +
  603. + ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
  604. + (check_val == (value & check_val)), 100, 20000);
  605. + if (ret) {
  606. + dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
  607. + return ret;
  608. + }
  609. +
  610. + return 0;
  611. +}
  612. +
  613. +static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
  614. +{
  615. + struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
  616. + u32 value;
  617. + int ret;
  618. + int i;
  619. +
  620. + /* power down all u3 ports */
  621. + for (i = 0; i < mtk->num_u3_ports; i++) {
  622. + value = readl(&ippc->u3_ctrl_p[i]);
  623. + value |= CTRL_U3_PORT_PDN;
  624. + writel(value, &ippc->u3_ctrl_p[i]);
  625. + }
  626. +
  627. + /* power down all u2 ports */
  628. + for (i = 0; i < mtk->num_u2_ports; i++) {
  629. + value = readl(&ippc->u2_ctrl_p[i]);
  630. + value |= CTRL_U2_PORT_PDN;
  631. + writel(value, &ippc->u2_ctrl_p[i]);
  632. + }
  633. +
  634. + /* power down host ip */
  635. + value = readl(&ippc->ip_pw_ctr1);
  636. + value |= CTRL1_IP_HOST_PDN;
  637. + writel(value, &ippc->ip_pw_ctr1);
  638. +
  639. + /* wait for host ip to sleep */
  640. + ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
  641. + (value & STS1_IP_SLEEP_STS), 100, 100000);
  642. + if (ret) {
  643. + dev_err(mtk->dev, "ip sleep failed!!!\n");
  644. + return ret;
  645. + }
  646. + return 0;
  647. +}
  648. +
  649. +static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
  650. +{
  651. + struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
  652. + u32 value;
  653. +
  654. + /* reset whole ip */
  655. + value = readl(&ippc->ip_pw_ctr0);
  656. + value |= CTRL0_IP_SW_RST;
  657. + writel(value, &ippc->ip_pw_ctr0);
  658. + udelay(1);
  659. + value = readl(&ippc->ip_pw_ctr0);
  660. + value &= ~CTRL0_IP_SW_RST;
  661. + writel(value, &ippc->ip_pw_ctr0);
  662. +
  663. + /*
  664. + * device ip is default power-on in fact
  665. + * power down device ip, otherwise ip-sleep will fail
  666. + */
  667. + value = readl(&ippc->ip_pw_ctr2);
  668. + value |= CTRL2_IP_DEV_PDN;
  669. + writel(value, &ippc->ip_pw_ctr2);
  670. +
  671. + value = readl(&ippc->ip_xhci_cap);
  672. + mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
  673. + mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
  674. + dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
  675. + mtk->num_u2_ports, mtk->num_u3_ports);
  676. +
  677. + return xhci_mtk_host_enable(mtk);
  678. +}
  679. +
  680. +static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
  681. +{
  682. + int ret;
  683. +
  684. + ret = clk_prepare_enable(mtk->sys_clk);
  685. + if (ret) {
  686. + dev_err(mtk->dev, "failed to enable sys_clk\n");
  687. + goto sys_clk_err;
  688. + }
  689. +
  690. + if (mtk->wakeup_src) {
  691. + ret = clk_prepare_enable(mtk->wk_deb_p0);
  692. + if (ret) {
  693. + dev_err(mtk->dev, "failed to enable wk_deb_p0\n");
  694. + goto usb_p0_err;
  695. + }
  696. +
  697. + ret = clk_prepare_enable(mtk->wk_deb_p1);
  698. + if (ret) {
  699. + dev_err(mtk->dev, "failed to enable wk_deb_p1\n");
  700. + goto usb_p1_err;
  701. + }
  702. + }
  703. + return 0;
  704. +
  705. +usb_p1_err:
  706. + clk_disable_unprepare(mtk->wk_deb_p0);
  707. +usb_p0_err:
  708. + clk_disable_unprepare(mtk->sys_clk);
  709. +sys_clk_err:
  710. + return -EINVAL;
  711. +}
  712. +
  713. +static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
  714. +{
  715. + if (mtk->wakeup_src) {
  716. + clk_disable_unprepare(mtk->wk_deb_p1);
  717. + clk_disable_unprepare(mtk->wk_deb_p0);
  718. + }
  719. + clk_disable_unprepare(mtk->sys_clk);
  720. +}
  721. +
  722. +/* only clocks can be turn off for ip-sleep wakeup mode */
  723. +static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk *mtk)
  724. +{
  725. + u32 tmp;
  726. + struct regmap *pericfg = mtk->pericfg;
  727. +
  728. + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
  729. + tmp &= ~UWK_CTL1_IS_P;
  730. + tmp &= ~(UWK_CTL1_IS_C(0xf));
  731. + tmp |= UWK_CTL1_IS_C(0x8);
  732. + regmap_write(pericfg, PERI_WK_CTRL1, tmp);
  733. + regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
  734. +
  735. + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
  736. + dev_dbg(mtk->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n",
  737. + __func__, tmp);
  738. +}
  739. +
  740. +static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk *mtk)
  741. +{
  742. + u32 tmp;
  743. +
  744. + regmap_read(mtk->pericfg, PERI_WK_CTRL1, &tmp);
  745. + tmp &= ~UWK_CTL1_IS_E;
  746. + regmap_write(mtk->pericfg, PERI_WK_CTRL1, tmp);
  747. +}
  748. +
  749. +/*
  750. +* for line-state wakeup mode, phy's power should not power-down
  751. +* and only support cable plug in/out
  752. +*/
  753. +static void usb_wakeup_line_state_en(struct xhci_hcd_mtk *mtk)
  754. +{
  755. + u32 tmp;
  756. + struct regmap *pericfg = mtk->pericfg;
  757. +
  758. + /* line-state of u2-port0 */
  759. + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
  760. + tmp &= ~UWK_CTL1_0P_LS_P;
  761. + tmp &= ~(UWK_CTL1_0P_LS_C(0xf));
  762. + tmp |= UWK_CTL1_0P_LS_C(0x8);
  763. + regmap_write(pericfg, PERI_WK_CTRL1, tmp);
  764. + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
  765. + regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E);
  766. +
  767. + /* line-state of u2-port1 */
  768. + regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
  769. + tmp &= ~(UWK_CTL1_1P_LS_C(0xf));
  770. + tmp |= UWK_CTL1_1P_LS_C(0x8);
  771. + regmap_write(pericfg, PERI_WK_CTRL0, tmp);
  772. + regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E);
  773. +}
  774. +
  775. +static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk *mtk)
  776. +{
  777. + u32 tmp;
  778. + struct regmap *pericfg = mtk->pericfg;
  779. +
  780. + /* line-state of u2-port0 */
  781. + regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
  782. + tmp &= ~UWK_CTL1_0P_LS_E;
  783. + regmap_write(pericfg, PERI_WK_CTRL1, tmp);
  784. +
  785. + /* line-state of u2-port1 */
  786. + regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
  787. + tmp &= ~UWK_CTL1_1P_LS_E;
  788. + regmap_write(pericfg, PERI_WK_CTRL0, tmp);
  789. +}
  790. +
  791. +static void usb_wakeup_enable(struct xhci_hcd_mtk *mtk)
  792. +{
  793. + if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
  794. + usb_wakeup_ip_sleep_en(mtk);
  795. + else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
  796. + usb_wakeup_line_state_en(mtk);
  797. +}
  798. +
  799. +static void usb_wakeup_disable(struct xhci_hcd_mtk *mtk)
  800. +{
  801. + if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
  802. + usb_wakeup_ip_sleep_dis(mtk);
  803. + else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
  804. + usb_wakeup_line_state_dis(mtk);
  805. +}
  806. +
  807. +static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
  808. + struct device_node *dn)
  809. +{
  810. + struct device *dev = mtk->dev;
  811. +
  812. + /*
  813. + * wakeup function is optional, so it is not an error if this property
  814. + * does not exist, and in such case, no need to get relative
  815. + * properties anymore.
  816. + */
  817. + of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src);
  818. + if (!mtk->wakeup_src)
  819. + return 0;
  820. +
  821. + mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
  822. + if (IS_ERR(mtk->wk_deb_p0)) {
  823. + dev_err(dev, "fail to get wakeup_deb_p0\n");
  824. + return PTR_ERR(mtk->wk_deb_p0);
  825. + }
  826. +
  827. + mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
  828. + if (IS_ERR(mtk->wk_deb_p1)) {
  829. + dev_err(dev, "fail to get wakeup_deb_p1\n");
  830. + return PTR_ERR(mtk->wk_deb_p1);
  831. + }
  832. +
  833. + mtk->pericfg = syscon_regmap_lookup_by_phandle(dn,
  834. + "mediatek,syscon-wakeup");
  835. + if (IS_ERR(mtk->pericfg)) {
  836. + dev_err(dev, "fail to get pericfg regs\n");
  837. + return PTR_ERR(mtk->pericfg);
  838. + }
  839. +
  840. + return 0;
  841. +}
  842. +
  843. +static int xhci_mtk_setup(struct usb_hcd *hcd);
  844. +static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
  845. + .extra_priv_size = sizeof(struct xhci_hcd),
  846. + .reset = xhci_mtk_setup,
  847. +};
  848. +
  849. +static struct hc_driver __read_mostly xhci_mtk_hc_driver;
  850. +
  851. +static int xhci_mtk_phy_init(struct xhci_hcd_mtk *mtk)
  852. +{
  853. + int i;
  854. + int ret;
  855. +
  856. + for (i = 0; i < mtk->num_phys; i++) {
  857. + ret = phy_init(mtk->phys[i]);
  858. + if (ret)
  859. + goto exit_phy;
  860. + }
  861. + return 0;
  862. +
  863. +exit_phy:
  864. + for (; i > 0; i--)
  865. + phy_exit(mtk->phys[i - 1]);
  866. +
  867. + return ret;
  868. +}
  869. +
  870. +static int xhci_mtk_phy_exit(struct xhci_hcd_mtk *mtk)
  871. +{
  872. + int i;
  873. +
  874. + for (i = 0; i < mtk->num_phys; i++)
  875. + phy_exit(mtk->phys[i]);
  876. +
  877. + return 0;
  878. +}
  879. +
  880. +static int xhci_mtk_phy_power_on(struct xhci_hcd_mtk *mtk)
  881. +{
  882. + int i;
  883. + int ret;
  884. +
  885. + for (i = 0; i < mtk->num_phys; i++) {
  886. + ret = phy_power_on(mtk->phys[i]);
  887. + if (ret)
  888. + goto power_off_phy;
  889. + }
  890. + return 0;
  891. +
  892. +power_off_phy:
  893. + for (; i > 0; i--)
  894. + phy_power_off(mtk->phys[i - 1]);
  895. +
  896. + return ret;
  897. +}
  898. +
  899. +static void xhci_mtk_phy_power_off(struct xhci_hcd_mtk *mtk)
  900. +{
  901. + unsigned int i;
  902. +
  903. + for (i = 0; i < mtk->num_phys; i++)
  904. + phy_power_off(mtk->phys[i]);
  905. +}
  906. +
  907. +static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
  908. +{
  909. + int ret;
  910. +
  911. + ret = regulator_enable(mtk->vbus);
  912. + if (ret) {
  913. + dev_err(mtk->dev, "failed to enable vbus\n");
  914. + return ret;
  915. + }
  916. +
  917. + ret = regulator_enable(mtk->vusb33);
  918. + if (ret) {
  919. + dev_err(mtk->dev, "failed to enable vusb33\n");
  920. + regulator_disable(mtk->vbus);
  921. + return ret;
  922. + }
  923. + return 0;
  924. +}
  925. +
  926. +static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
  927. +{
  928. + regulator_disable(mtk->vbus);
  929. + regulator_disable(mtk->vusb33);
  930. +}
  931. +
  932. +static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
  933. +{
  934. + struct usb_hcd *hcd = xhci_to_hcd(xhci);
  935. + struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
  936. +
  937. + /*
  938. + * As of now platform drivers don't provide MSI support so we ensure
  939. + * here that the generic code does not try to make a pci_dev from our
  940. + * dev struct in order to setup MSI
  941. + */
  942. + xhci->quirks |= XHCI_PLAT;
  943. + xhci->quirks |= XHCI_MTK_HOST;
  944. + /*
  945. + * MTK host controller gives a spurious successful event after a
  946. + * short transfer. Ignore it.
  947. + */
  948. + xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
  949. + if (mtk->lpm_support)
  950. + xhci->quirks |= XHCI_LPM_SUPPORT;
  951. +}
  952. +
  953. +/* called during probe() after chip reset completes */
  954. +static int xhci_mtk_setup(struct usb_hcd *hcd)
  955. +{
  956. + struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
  957. + int ret;
  958. +
  959. + if (usb_hcd_is_primary_hcd(hcd)) {
  960. + ret = xhci_mtk_ssusb_config(mtk);
  961. + if (ret)
  962. + return ret;
  963. + ret = xhci_mtk_sch_init(mtk);
  964. + if (ret)
  965. + return ret;
  966. + }
  967. +
  968. + return xhci_gen_setup(hcd, xhci_mtk_quirks);
  969. +}
  970. +
  971. +static int xhci_mtk_probe(struct platform_device *pdev)
  972. +{
  973. + struct device *dev = &pdev->dev;
  974. + struct device_node *node = dev->of_node;
  975. + struct xhci_hcd_mtk *mtk;
  976. + const struct hc_driver *driver;
  977. + struct xhci_hcd *xhci;
  978. + struct resource *res;
  979. + struct usb_hcd *hcd;
  980. + struct phy *phy;
  981. + int phy_num;
  982. + int ret = -ENODEV;
  983. + int irq;
  984. +
  985. + if (usb_disabled())
  986. + return -ENODEV;
  987. +
  988. + driver = &xhci_mtk_hc_driver;
  989. + mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
  990. + if (!mtk)
  991. + return -ENOMEM;
  992. +
  993. + mtk->dev = dev;
  994. + mtk->vbus = devm_regulator_get(dev, "vbus");
  995. + if (IS_ERR(mtk->vbus)) {
  996. + dev_err(dev, "fail to get vbus\n");
  997. + return PTR_ERR(mtk->vbus);
  998. + }
  999. +
  1000. + mtk->vusb33 = devm_regulator_get(dev, "vusb33");
  1001. + if (IS_ERR(mtk->vusb33)) {
  1002. + dev_err(dev, "fail to get vusb33\n");
  1003. + return PTR_ERR(mtk->vusb33);
  1004. + }
  1005. +
  1006. + mtk->sys_clk = devm_clk_get(dev, "sys_ck");
  1007. + if (IS_ERR(mtk->sys_clk)) {
  1008. + dev_err(dev, "fail to get sys_ck\n");
  1009. + return PTR_ERR(mtk->sys_clk);
  1010. + }
  1011. +
  1012. + mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
  1013. +
  1014. + ret = usb_wakeup_of_property_parse(mtk, node);
  1015. + if (ret)
  1016. + return ret;
  1017. +
  1018. + mtk->num_phys = of_count_phandle_with_args(node,
  1019. + "phys", "#phy-cells");
  1020. + if (mtk->num_phys > 0) {
  1021. + mtk->phys = devm_kcalloc(dev, mtk->num_phys,
  1022. + sizeof(*mtk->phys), GFP_KERNEL);
  1023. + if (!mtk->phys)
  1024. + return -ENOMEM;
  1025. + } else {
  1026. + mtk->num_phys = 0;
  1027. + }
  1028. + pm_runtime_enable(dev);
  1029. + pm_runtime_get_sync(dev);
  1030. + device_enable_async_suspend(dev);
  1031. +
  1032. + ret = xhci_mtk_ldos_enable(mtk);
  1033. + if (ret)
  1034. + goto disable_pm;
  1035. +
  1036. + ret = xhci_mtk_clks_enable(mtk);
  1037. + if (ret)
  1038. + goto disable_ldos;
  1039. +
  1040. + irq = platform_get_irq(pdev, 0);
  1041. + if (irq < 0)
  1042. + goto disable_clk;
  1043. +
  1044. + /* Initialize dma_mask and coherent_dma_mask to 32-bits */
  1045. + ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
  1046. + if (ret)
  1047. + goto disable_clk;
  1048. +
  1049. + if (!dev->dma_mask)
  1050. + dev->dma_mask = &dev->coherent_dma_mask;
  1051. + else
  1052. + dma_set_mask(dev, DMA_BIT_MASK(32));
  1053. +
  1054. + hcd = usb_create_hcd(driver, dev, dev_name(dev));
  1055. + if (!hcd) {
  1056. + ret = -ENOMEM;
  1057. + goto disable_clk;
  1058. + }
  1059. +
  1060. + /*
  1061. + * USB 2.0 roothub is stored in the platform_device.
  1062. + * Swap it with mtk HCD.
  1063. + */
  1064. + mtk->hcd = platform_get_drvdata(pdev);
  1065. + platform_set_drvdata(pdev, mtk);
  1066. +
  1067. + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1068. + hcd->regs = devm_ioremap_resource(dev, res);
  1069. + if (IS_ERR(hcd->regs)) {
  1070. + ret = PTR_ERR(hcd->regs);
  1071. + goto put_usb2_hcd;
  1072. + }
  1073. + hcd->rsrc_start = res->start;
  1074. + hcd->rsrc_len = resource_size(res);
  1075. +
  1076. + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1077. + mtk->ippc_regs = devm_ioremap_resource(dev, res);
  1078. + if (IS_ERR(mtk->ippc_regs)) {
  1079. + ret = PTR_ERR(mtk->ippc_regs);
  1080. + goto put_usb2_hcd;
  1081. + }
  1082. +
  1083. + for (phy_num = 0; phy_num < mtk->num_phys; phy_num++) {
  1084. + phy = devm_of_phy_get_by_index(dev, node, phy_num);
  1085. + if (IS_ERR(phy)) {
  1086. + ret = PTR_ERR(phy);
  1087. + goto put_usb2_hcd;
  1088. + }
  1089. + mtk->phys[phy_num] = phy;
  1090. + }
  1091. +
  1092. + ret = xhci_mtk_phy_init(mtk);
  1093. + if (ret)
  1094. + goto put_usb2_hcd;
  1095. +
  1096. + ret = xhci_mtk_phy_power_on(mtk);
  1097. + if (ret)
  1098. + goto exit_phys;
  1099. +
  1100. + device_init_wakeup(dev, true);
  1101. +
  1102. + xhci = hcd_to_xhci(hcd);
  1103. + xhci->main_hcd = hcd;
  1104. + xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
  1105. + dev_name(dev), hcd);
  1106. + if (!xhci->shared_hcd) {
  1107. + ret = -ENOMEM;
  1108. + goto power_off_phys;
  1109. + }
  1110. +
  1111. + if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
  1112. + xhci->shared_hcd->can_do_streams = 1;
  1113. +
  1114. + ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
  1115. + if (ret)
  1116. + goto put_usb3_hcd;
  1117. +
  1118. + ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
  1119. + if (ret)
  1120. + goto dealloc_usb2_hcd;
  1121. +
  1122. + return 0;
  1123. +
  1124. +dealloc_usb2_hcd:
  1125. + usb_remove_hcd(hcd);
  1126. +
  1127. +put_usb3_hcd:
  1128. + xhci_mtk_sch_exit(mtk);
  1129. + usb_put_hcd(xhci->shared_hcd);
  1130. +
  1131. +power_off_phys:
  1132. + xhci_mtk_phy_power_off(mtk);
  1133. + device_init_wakeup(dev, false);
  1134. +
  1135. +exit_phys:
  1136. + xhci_mtk_phy_exit(mtk);
  1137. +
  1138. +put_usb2_hcd:
  1139. + usb_put_hcd(hcd);
  1140. +
  1141. +disable_clk:
  1142. + xhci_mtk_clks_disable(mtk);
  1143. +
  1144. +disable_ldos:
  1145. + xhci_mtk_ldos_disable(mtk);
  1146. +
  1147. +disable_pm:
  1148. + pm_runtime_put_sync(dev);
  1149. + pm_runtime_disable(dev);
  1150. + return ret;
  1151. +}
  1152. +
  1153. +static int xhci_mtk_remove(struct platform_device *dev)
  1154. +{
  1155. + struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
  1156. + struct usb_hcd *hcd = mtk->hcd;
  1157. + struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1158. +
  1159. + usb_remove_hcd(xhci->shared_hcd);
  1160. + xhci_mtk_phy_power_off(mtk);
  1161. + xhci_mtk_phy_exit(mtk);
  1162. + device_init_wakeup(&dev->dev, false);
  1163. +
  1164. + usb_remove_hcd(hcd);
  1165. + usb_put_hcd(xhci->shared_hcd);
  1166. + usb_put_hcd(hcd);
  1167. + xhci_mtk_sch_exit(mtk);
  1168. + xhci_mtk_clks_disable(mtk);
  1169. + xhci_mtk_ldos_disable(mtk);
  1170. + pm_runtime_put_sync(&dev->dev);
  1171. + pm_runtime_disable(&dev->dev);
  1172. +
  1173. + return 0;
  1174. +}
  1175. +
  1176. +#ifdef CONFIG_PM_SLEEP
  1177. +static int xhci_mtk_suspend(struct device *dev)
  1178. +{
  1179. + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
  1180. +
  1181. + xhci_mtk_host_disable(mtk);
  1182. + xhci_mtk_phy_power_off(mtk);
  1183. + xhci_mtk_clks_disable(mtk);
  1184. + usb_wakeup_enable(mtk);
  1185. + return 0;
  1186. +}
  1187. +
  1188. +static int xhci_mtk_resume(struct device *dev)
  1189. +{
  1190. + struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
  1191. +
  1192. + usb_wakeup_disable(mtk);
  1193. + xhci_mtk_clks_enable(mtk);
  1194. + xhci_mtk_phy_power_on(mtk);
  1195. + xhci_mtk_host_enable(mtk);
  1196. + return 0;
  1197. +}
  1198. +
  1199. +static const struct dev_pm_ops xhci_mtk_pm_ops = {
  1200. + SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
  1201. +};
  1202. +#define DEV_PM_OPS (&xhci_mtk_pm_ops)
  1203. +#else
  1204. +#define DEV_PM_OPS NULL
  1205. +#endif /* CONFIG_PM */
  1206. +
  1207. +#ifdef CONFIG_OF
  1208. +static const struct of_device_id mtk_xhci_of_match[] = {
  1209. + { .compatible = "mediatek,mt8173-xhci"},
  1210. + { },
  1211. +};
  1212. +MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
  1213. +#endif
  1214. +
  1215. +static struct platform_driver mtk_xhci_driver = {
  1216. + .probe = xhci_mtk_probe,
  1217. + .remove = xhci_mtk_remove,
  1218. + .driver = {
  1219. + .name = "xhci-mtk",
  1220. + .pm = DEV_PM_OPS,
  1221. + .of_match_table = of_match_ptr(mtk_xhci_of_match),
  1222. + },
  1223. +};
  1224. +MODULE_ALIAS("platform:xhci-mtk");
  1225. +
  1226. +static int __init xhci_mtk_init(void)
  1227. +{
  1228. + xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
  1229. + return platform_driver_register(&mtk_xhci_driver);
  1230. +}
  1231. +module_init(xhci_mtk_init);
  1232. +
  1233. +static void __exit xhci_mtk_exit(void)
  1234. +{
  1235. + platform_driver_unregister(&mtk_xhci_driver);
  1236. +}
  1237. +module_exit(xhci_mtk_exit);
  1238. +
  1239. +MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
  1240. +MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
  1241. +MODULE_LICENSE("GPL v2");
  1242. --- /dev/null
  1243. +++ b/drivers/usb/host/xhci-mtk.h
  1244. @@ -0,0 +1,162 @@
  1245. +/*
  1246. + * Copyright (c) 2015 MediaTek Inc.
  1247. + * Author:
  1248. + * Zhigang.Wei <zhigang.wei@mediatek.com>
  1249. + * Chunfeng.Yun <chunfeng.yun@mediatek.com>
  1250. + *
  1251. + * This software is licensed under the terms of the GNU General Public
  1252. + * License version 2, as published by the Free Software Foundation, and
  1253. + * may be copied, distributed, and modified under those terms.
  1254. + *
  1255. + * This program is distributed in the hope that it will be useful,
  1256. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  1257. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  1258. + * GNU General Public License for more details.
  1259. + *
  1260. + */
  1261. +
  1262. +#ifndef _XHCI_MTK_H_
  1263. +#define _XHCI_MTK_H_
  1264. +
  1265. +#include "xhci.h"
  1266. +
  1267. +/**
  1268. + * To simplify scheduler algorithm, set a upper limit for ESIT,
  1269. + * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
  1270. + * round down to the limit value, that means allocating more
  1271. + * bandwidth to it.
  1272. + */
  1273. +#define XHCI_MTK_MAX_ESIT 64
  1274. +
  1275. +/**
  1276. + * struct mu3h_sch_bw_info: schedule information for bandwidth domain
  1277. + *
  1278. + * @bus_bw: array to keep track of bandwidth already used at each uframes
  1279. + * @bw_ep_list: eps in the bandwidth domain
  1280. + *
  1281. + * treat a HS root port as a bandwidth domain, but treat a SS root port as
  1282. + * two bandwidth domains, one for IN eps and another for OUT eps.
  1283. + */
  1284. +struct mu3h_sch_bw_info {
  1285. + u32 bus_bw[XHCI_MTK_MAX_ESIT];
  1286. + struct list_head bw_ep_list;
  1287. +};
  1288. +
  1289. +/**
  1290. + * struct mu3h_sch_ep_info: schedule information for endpoint
  1291. + *
  1292. + * @esit: unit is 125us, equal to 2 << Interval field in ep-context
  1293. + * @num_budget_microframes: number of continuous uframes
  1294. + * (@repeat==1) scheduled within the interval
  1295. + * @bw_cost_per_microframe: bandwidth cost per microframe
  1296. + * @endpoint: linked into bandwidth domain which it belongs to
  1297. + * @ep: address of usb_host_endpoint struct
  1298. + * @offset: which uframe of the interval that transfer should be
  1299. + * scheduled first time within the interval
  1300. + * @repeat: the time gap between two uframes that transfers are
  1301. + * scheduled within a interval. in the simple algorithm, only
  1302. + * assign 0 or 1 to it; 0 means using only one uframe in a
  1303. + * interval, and 1 means using @num_budget_microframes
  1304. + * continuous uframes
  1305. + * @pkts: number of packets to be transferred in the scheduled uframes
  1306. + * @cs_count: number of CS that host will trigger
  1307. + * @burst_mode: burst mode for scheduling. 0: normal burst mode,
  1308. + * distribute the bMaxBurst+1 packets for a single burst
  1309. + * according to @pkts and @repeat, repeate the burst multiple
  1310. + * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
  1311. + * according to @pkts and @repeat. normal mode is used by
  1312. + * default
  1313. + */
  1314. +struct mu3h_sch_ep_info {
  1315. + u32 esit;
  1316. + u32 num_budget_microframes;
  1317. + u32 bw_cost_per_microframe;
  1318. + struct list_head endpoint;
  1319. + void *ep;
  1320. + /*
  1321. + * mtk xHCI scheduling information put into reserved DWs
  1322. + * in ep context
  1323. + */
  1324. + u32 offset;
  1325. + u32 repeat;
  1326. + u32 pkts;
  1327. + u32 cs_count;
  1328. + u32 burst_mode;
  1329. +};
  1330. +
  1331. +#define MU3C_U3_PORT_MAX 4
  1332. +#define MU3C_U2_PORT_MAX 5
  1333. +
  1334. +/**
  1335. + * struct mu3c_ippc_regs: MTK ssusb ip port control registers
  1336. + * @ip_pw_ctr0~3: ip power and clock control registers
  1337. + * @ip_pw_sts1~2: ip power and clock status registers
  1338. + * @ip_xhci_cap: ip xHCI capability register
  1339. + * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
  1340. + * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
  1341. + * @u2_phy_pll: usb2 phy pll control register
  1342. + */
  1343. +struct mu3c_ippc_regs {
  1344. + __le32 ip_pw_ctr0;
  1345. + __le32 ip_pw_ctr1;
  1346. + __le32 ip_pw_ctr2;
  1347. + __le32 ip_pw_ctr3;
  1348. + __le32 ip_pw_sts1;
  1349. + __le32 ip_pw_sts2;
  1350. + __le32 reserved0[3];
  1351. + __le32 ip_xhci_cap;
  1352. + __le32 reserved1[2];
  1353. + __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
  1354. + __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
  1355. + __le32 reserved2;
  1356. + __le32 u2_phy_pll;
  1357. + __le32 reserved3[33]; /* 0x80 ~ 0xff */
  1358. +};
  1359. +
  1360. +struct xhci_hcd_mtk {
  1361. + struct device *dev;
  1362. + struct usb_hcd *hcd;
  1363. + struct mu3h_sch_bw_info *sch_array;
  1364. + struct mu3c_ippc_regs __iomem *ippc_regs;
  1365. + int num_u2_ports;
  1366. + int num_u3_ports;
  1367. + struct regulator *vusb33;
  1368. + struct regulator *vbus;
  1369. + struct clk *sys_clk; /* sys and mac clock */
  1370. + struct clk *wk_deb_p0; /* port0's wakeup debounce clock */
  1371. + struct clk *wk_deb_p1;
  1372. + struct regmap *pericfg;
  1373. + struct phy **phys;
  1374. + int num_phys;
  1375. + int wakeup_src;
  1376. + bool lpm_support;
  1377. +};
  1378. +
  1379. +static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
  1380. +{
  1381. + return dev_get_drvdata(hcd->self.controller);
  1382. +}
  1383. +
  1384. +#if IS_ENABLED(CONFIG_USB_XHCI_MTK)
  1385. +int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
  1386. +void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
  1387. +int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
  1388. + struct usb_host_endpoint *ep);
  1389. +void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
  1390. + struct usb_host_endpoint *ep);
  1391. +
  1392. +#else
  1393. +static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
  1394. + struct usb_device *udev, struct usb_host_endpoint *ep)
  1395. +{
  1396. + return 0;
  1397. +}
  1398. +
  1399. +static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
  1400. + struct usb_device *udev, struct usb_host_endpoint *ep)
  1401. +{
  1402. +}
  1403. +
  1404. +#endif
  1405. +
  1406. +#endif /* _XHCI_MTK_H_ */
  1407. --- a/drivers/usb/host/xhci-ring.c
  1408. +++ b/drivers/usb/host/xhci-ring.c
  1409. @@ -68,6 +68,7 @@
  1410. #include <linux/slab.h>
  1411. #include "xhci.h"
  1412. #include "xhci-trace.h"
  1413. +#include "xhci-mtk.h"
  1414. /*
  1415. * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  1416. @@ -3110,17 +3111,22 @@ static u32 xhci_td_remainder(struct xhci
  1417. {
  1418. u32 maxp, total_packet_count;
  1419. - if (xhci->hci_version < 0x100)
  1420. + /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */
  1421. + if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
  1422. return ((td_total_len - transferred) >> 10);
  1423. - maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
  1424. - total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
  1425. -
  1426. /* One TRB with a zero-length data packet. */
  1427. if (num_trbs_left == 0 || (transferred == 0 && trb_buff_len == 0) ||
  1428. trb_buff_len == td_total_len)
  1429. return 0;
  1430. + /* for MTK xHCI, TD size doesn't include this TRB */
  1431. + if (xhci->quirks & XHCI_MTK_HOST)
  1432. + trb_buff_len = 0;
  1433. +
  1434. + maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
  1435. + total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
  1436. +
  1437. /* Queueing functions don't count the current TRB into transferred */
  1438. return (total_packet_count - ((transferred + trb_buff_len) / maxp));
  1439. }
  1440. @@ -3508,7 +3514,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
  1441. field |= 0x1;
  1442. /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
  1443. - if (xhci->hci_version >= 0x100) {
  1444. + if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
  1445. if (urb->transfer_buffer_length > 0) {
  1446. if (setup->bRequestType & USB_DIR_IN)
  1447. field |= TRB_TX_TYPE(TRB_DATA_IN);
  1448. --- a/drivers/usb/host/xhci.c
  1449. +++ b/drivers/usb/host/xhci.c
  1450. @@ -31,6 +31,7 @@
  1451. #include "xhci.h"
  1452. #include "xhci-trace.h"
  1453. +#include "xhci-mtk.h"
  1454. #define DRIVER_AUTHOR "Sarah Sharp"
  1455. #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
  1456. @@ -635,7 +636,11 @@ int xhci_run(struct usb_hcd *hcd)
  1457. "// Set the interrupt modulation register");
  1458. temp = readl(&xhci->ir_set->irq_control);
  1459. temp &= ~ER_IRQ_INTERVAL_MASK;
  1460. - temp |= (u32) 160;
  1461. + /*
  1462. + * the increment interval is 8 times as much as that defined
  1463. + * in xHCI spec on MTK's controller
  1464. + */
  1465. + temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
  1466. writel(temp, &xhci->ir_set->irq_control);
  1467. /* Set the HCD state before we enable the irqs */
  1468. @@ -1691,6 +1696,9 @@ int xhci_drop_endpoint(struct usb_hcd *h
  1469. xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
  1470. + if (xhci->quirks & XHCI_MTK_HOST)
  1471. + xhci_mtk_drop_ep_quirk(hcd, udev, ep);
  1472. +
  1473. xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
  1474. (unsigned int) ep->desc.bEndpointAddress,
  1475. udev->slot_id,
  1476. @@ -1786,6 +1794,15 @@ int xhci_add_endpoint(struct usb_hcd *hc
  1477. return -ENOMEM;
  1478. }
  1479. + if (xhci->quirks & XHCI_MTK_HOST) {
  1480. + ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
  1481. + if (ret < 0) {
  1482. + xhci_free_or_cache_endpoint_ring(xhci,
  1483. + virt_dev, ep_index);
  1484. + return ret;
  1485. + }
  1486. + }
  1487. +
  1488. ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
  1489. new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
  1490. --- a/drivers/usb/host/xhci.h
  1491. +++ b/drivers/usb/host/xhci.h
  1492. @@ -1634,6 +1634,7 @@ struct xhci_hcd {
  1493. /* For controllers with a broken beyond repair streams implementation */
  1494. #define XHCI_BROKEN_STREAMS (1 << 19)
  1495. #define XHCI_PME_STUCK_QUIRK (1 << 20)
  1496. +#define XHCI_MTK_HOST (1 << 21)
  1497. #define XHCI_MISSING_CAS (1 << 24)
  1498. unsigned int num_active_eps;
  1499. unsigned int limit_active_eps;