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0507-net-next-mediatek-add-support-for-rt3883.patch 2.8 KB

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  1. From 5ad283c69029a519681ed453e7f7ddf250c10559 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Wed, 18 Nov 2015 03:51:24 +0100
  4. Subject: [PATCH 507/513] net-next: mediatek: add support for rt3883
  5. Add support for rt3883 and its smaller version rt3662. They both have a single
  6. gBit port that will normally be attached to an external phy of switch.
  7. Signed-off-by: John Crispin <blogic@openwrt.org>
  8. Signed-off-by: Felix Fietkau <nbd@nbd.name>
  9. Signed-off-by: Michael Lee <igvtee@gmail.com>
  10. ---
  11. drivers/net/ethernet/mediatek/soc_rt3883.c | 75 ++++++++++++++++++++++++++++
  12. 1 file changed, 75 insertions(+)
  13. create mode 100644 drivers/net/ethernet/mediatek/soc_rt3883.c
  14. --- /dev/null
  15. +++ b/drivers/net/ethernet/mediatek/soc_rt3883.c
  16. @@ -0,0 +1,75 @@
  17. +/* This program is free software; you can redistribute it and/or modify
  18. + * it under the terms of the GNU General Public License as published by
  19. + * the Free Software Foundation; version 2 of the License
  20. + *
  21. + * This program is distributed in the hope that it will be useful,
  22. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. + * GNU General Public License for more details.
  25. + *
  26. + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  27. + * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  28. + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  29. + */
  30. +
  31. +#include <linux/module.h>
  32. +
  33. +#include <asm/mach-ralink/ralink_regs.h>
  34. +
  35. +#include "mtk_eth_soc.h"
  36. +#include "mdio_rt2880.h"
  37. +
  38. +#define RT3883_RSTCTRL_FE BIT(21)
  39. +
  40. +static void rt3883_fe_reset(void)
  41. +{
  42. + fe_reset(RT3883_RSTCTRL_FE);
  43. +}
  44. +
  45. +static int rt3883_fwd_config(struct fe_priv *priv)
  46. +{
  47. + int ret;
  48. +
  49. + ret = fe_set_clock_cycle(priv);
  50. + if (ret)
  51. + return ret;
  52. +
  53. + fe_fwd_config(priv);
  54. + fe_w32(FE_PSE_FQFC_CFG_256Q, FE_PSE_FQ_CFG);
  55. + fe_csum_config(priv);
  56. +
  57. + return ret;
  58. +}
  59. +
  60. +static void rt3883_init_data(struct fe_soc_data *data,
  61. + struct net_device *netdev)
  62. +{
  63. + struct fe_priv *priv = netdev_priv(netdev);
  64. +
  65. + priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
  66. + FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
  67. + netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
  68. + NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
  69. +}
  70. +
  71. +static struct fe_soc_data rt3883_data = {
  72. + .init_data = rt3883_init_data,
  73. + .reset_fe = rt3883_fe_reset,
  74. + .fwd_config = rt3883_fwd_config,
  75. + .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
  76. + .rx_int = FE_RX_DONE_INT,
  77. + .tx_int = FE_TX_DONE_INT,
  78. + .status_int = FE_CNT_GDM_AF,
  79. + .checksum_bit = RX_DMA_L4VALID,
  80. + .mdio_read = rt2880_mdio_read,
  81. + .mdio_write = rt2880_mdio_write,
  82. + .mdio_adjust_link = rt2880_mdio_link_adjust,
  83. + .port_init = rt2880_port_init,
  84. +};
  85. +
  86. +const struct of_device_id of_fe_match[] = {
  87. + { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
  88. + {},
  89. +};
  90. +
  91. +MODULE_DEVICE_TABLE(of, of_fe_match);