0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch 33 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181
  1. From cf5a08f1f16913da8bb24a96afaa2969b29d0827 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Mon, 14 Dec 2015 22:25:57 +0100
  4. Subject: [PATCH 513/513] net: mediatek: add swconfig driver for gsw_mt762x
  5. Signed-off-by: John Crispin <blogic@openwrt.org>
  6. ---
  7. drivers/net/ethernet/mediatek/Makefile | 4 +-
  8. drivers/net/ethernet/mediatek/gsw_mt7620.c | 3 +
  9. drivers/net/ethernet/mediatek/gsw_mt7620.h | 3 +
  10. drivers/net/ethernet/mediatek/mt7530.c | 884 ++++++++++++++++++++++++++++
  11. drivers/net/ethernet/mediatek/mt7530.h | 186 ++++++
  12. drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 +-
  13. drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
  14. drivers/net/ethernet/mediatek/soc_mt7620.c | 1 +
  15. 8 files changed, 1087 insertions(+), 4 deletions(-)
  16. create mode 100644 drivers/net/ethernet/mediatek/mt7530.c
  17. create mode 100644 drivers/net/ethernet/mediatek/mt7530.h
  18. --- a/drivers/net/ethernet/mediatek/Makefile
  19. +++ b/drivers/net/ethernet/mediatek/Makefile
  20. @@ -15,6 +15,6 @@ mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7620
  21. mtk-eth-soc-$(CONFIG_NET_MEDIATEK_MT7621) += soc_mt7621.o
  22. obj-$(CONFIG_NET_MEDIATEK_ESW_RT3050) += esw_rt3050.o
  23. -obj-$(CONFIG_NET_MEDIATEK_GSW_MT7620) += gsw_mt7620.o
  24. -obj-$(CONFIG_NET_MEDIATEK_GSW_MT7621) += gsw_mt7621.o
  25. +obj-$(CONFIG_NET_MEDIATEK_GSW_MT7620) += gsw_mt7620.o mt7530.o
  26. +obj-$(CONFIG_NET_MEDIATEK_GSW_MT7621) += gsw_mt7621.o mt7530.o
  27. obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk-eth-soc.o
  28. --- a/drivers/net/ethernet/mediatek/gsw_mt7620.c
  29. +++ b/drivers/net/ethernet/mediatek/gsw_mt7620.c
  30. @@ -67,6 +67,9 @@ static void mt7620_hw_init(struct mt7620
  31. rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
  32. mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
  33. + /* Enable MIB stats */
  34. + mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
  35. +
  36. if (of_property_read_bool(np, "mediatek,mt7530")) {
  37. u32 val;
  38. --- a/drivers/net/ethernet/mediatek/gsw_mt7620.h
  39. +++ b/drivers/net/ethernet/mediatek/gsw_mt7620.h
  40. @@ -35,6 +35,8 @@
  41. #define GSW_MDIO_ADDR_SHIFT 20
  42. #define GSW_MDIO_REG_SHIFT 25
  43. +#define GSW_REG_MIB_CNT_EN 0x4000
  44. +
  45. #define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
  46. #define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
  47. #define GSW_REG_SMACCR0 0x3fE4
  48. @@ -76,6 +78,7 @@
  49. #define PHY_PRE_EN BIT(30)
  50. #define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
  51. +
  52. enum {
  53. /* Global attributes. */
  54. GSW_ATTR_ENABLE_VLAN,
  55. --- /dev/null
  56. +++ b/drivers/net/ethernet/mediatek/mt7530.c
  57. @@ -0,0 +1,890 @@
  58. +/*
  59. + * This program is free software; you can redistribute it and/or
  60. + * modify it under the terms of the GNU General Public License
  61. + * as published by the Free Software Foundation; either version 2
  62. + * of the License, or (at your option) any later version.
  63. + *
  64. + * This program is distributed in the hope that it will be useful,
  65. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  66. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  67. + * GNU General Public License for more details.
  68. + *
  69. + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  70. + * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
  71. + */
  72. +
  73. +#include <linux/if.h>
  74. +#include <linux/module.h>
  75. +#include <linux/init.h>
  76. +#include <linux/list.h>
  77. +#include <linux/if_ether.h>
  78. +#include <linux/skbuff.h>
  79. +#include <linux/netdevice.h>
  80. +#include <linux/netlink.h>
  81. +#include <linux/bitops.h>
  82. +#include <net/genetlink.h>
  83. +#include <linux/switch.h>
  84. +#include <linux/delay.h>
  85. +#include <linux/phy.h>
  86. +#include <linux/netdevice.h>
  87. +#include <linux/etherdevice.h>
  88. +#include <linux/lockdep.h>
  89. +#include <linux/workqueue.h>
  90. +#include <linux/of_device.h>
  91. +
  92. +#include "mt7530.h"
  93. +
  94. +#define MT7530_CPU_PORT 6
  95. +#define MT7530_NUM_PORTS 8
  96. +#ifdef CONFIG_SOC_MT7621
  97. +#define MT7530_NUM_VLANS 4095
  98. +#else
  99. +#define MT7530_NUM_VLANS 16
  100. +#endif
  101. +#define MT7530_MAX_VID 4095
  102. +#define MT7530_MIN_VID 0
  103. +
  104. +/* registers */
  105. +#define REG_ESW_VLAN_VTCR 0x90
  106. +#define REG_ESW_VLAN_VAWD1 0x94
  107. +#define REG_ESW_VLAN_VAWD2 0x98
  108. +#define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
  109. +
  110. +#define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
  111. +#define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
  112. +#define REG_ESW_VLAN_VAWD1_VALID BIT(0)
  113. +
  114. +/* vlan egress mode */
  115. +enum {
  116. + ETAG_CTRL_UNTAG = 0,
  117. + ETAG_CTRL_TAG = 2,
  118. + ETAG_CTRL_SWAP = 1,
  119. + ETAG_CTRL_STACK = 3,
  120. +};
  121. +
  122. +#define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
  123. +#define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
  124. +#define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
  125. +
  126. +#define REG_HWTRAP 0x7804
  127. +
  128. +#define MIB_DESC(_s , _o, _n) \
  129. + { \
  130. + .size = (_s), \
  131. + .offset = (_o), \
  132. + .name = (_n), \
  133. + }
  134. +
  135. +struct mt7xxx_mib_desc {
  136. + unsigned int size;
  137. + unsigned int offset;
  138. + const char *name;
  139. +};
  140. +
  141. +static const struct mt7xxx_mib_desc mt7620_mibs[] = {
  142. + MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0, "PPE_AC_BCNT0"),
  143. + MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0, "PPE_AC_PCNT0"),
  144. + MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63, "PPE_AC_BCNT63"),
  145. + MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63, "PPE_AC_PCNT63"),
  146. + MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0, "PPE_MTR_CNT0"),
  147. + MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63, "PPE_MTR_CNT63"),
  148. + MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT, "GDM1_TX_GBCNT"),
  149. + MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT, "GDM1_TX_GPCNT"),
  150. + MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT, "GDM1_TX_SKIPCNT"),
  151. + MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT, "GDM1_TX_COLCNT"),
  152. + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1, "GDM1_RX_GBCNT1"),
  153. + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1, "GDM1_RX_GPCNT1"),
  154. + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT, "GDM1_RX_OERCNT"),
  155. + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT, "GDM1_RX_FERCNT"),
  156. + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT, "GDM1_RX_SERCNT"),
  157. + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT, "GDM1_RX_LERCNT"),
  158. + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT, "GDM1_RX_CERCNT"),
  159. + MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT, "GDM1_RX_FCCNT"),
  160. + MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT, "GDM2_TX_GBCNT"),
  161. + MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT, "GDM2_TX_GPCNT"),
  162. + MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT, "GDM2_TX_SKIPCNT"),
  163. + MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT, "GDM2_TX_COLCNT"),
  164. + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT, "GDM2_RX_GBCNT"),
  165. + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT, "GDM2_RX_GPCNT"),
  166. + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT, "GDM2_RX_OERCNT"),
  167. + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT, "GDM2_RX_FERCNT"),
  168. + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT, "GDM2_RX_SERCNT"),
  169. + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT, "GDM2_RX_LERCNT"),
  170. + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT, "GDM2_RX_CERCNT"),
  171. + MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT, "GDM2_RX_FCCNT")
  172. +};
  173. +
  174. +static const struct mt7xxx_mib_desc mt7620_port_mibs[] = {
  175. + MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN, "TxGPC"),
  176. + MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN, "TxBOC"),
  177. + MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN, "TxGOC"),
  178. + MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN, "TxEPC"),
  179. + MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN, "RxGPC"),
  180. + MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN, "RxBOC"),
  181. + MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN, "RxGOC"),
  182. + MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N, "RxEPC1"),
  183. + MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N, "RxEPC2")
  184. +};
  185. +
  186. +static const struct mt7xxx_mib_desc mt7621_mibs[] = {
  187. + MIB_DESC(1, MT7621_STATS_TDPC, "TxDrop"),
  188. + MIB_DESC(1, MT7621_STATS_TCRC, "TxCRC"),
  189. + MIB_DESC(1, MT7621_STATS_TUPC, "TxUni"),
  190. + MIB_DESC(1, MT7621_STATS_TMPC, "TxMulti"),
  191. + MIB_DESC(1, MT7621_STATS_TBPC, "TxBroad"),
  192. + MIB_DESC(1, MT7621_STATS_TCEC, "TxCollision"),
  193. + MIB_DESC(1, MT7621_STATS_TSCEC, "TxSingleCol"),
  194. + MIB_DESC(1, MT7621_STATS_TMCEC, "TxMultiCol"),
  195. + MIB_DESC(1, MT7621_STATS_TDEC, "TxDefer"),
  196. + MIB_DESC(1, MT7621_STATS_TLCEC, "TxLateCol"),
  197. + MIB_DESC(1, MT7621_STATS_TXCEC, "TxExcCol"),
  198. + MIB_DESC(1, MT7621_STATS_TPPC, "TxPause"),
  199. + MIB_DESC(1, MT7621_STATS_TL64PC, "Tx64Byte"),
  200. + MIB_DESC(1, MT7621_STATS_TL65PC, "Tx65Byte"),
  201. + MIB_DESC(1, MT7621_STATS_TL128PC, "Tx128Byte"),
  202. + MIB_DESC(1, MT7621_STATS_TL256PC, "Tx256Byte"),
  203. + MIB_DESC(1, MT7621_STATS_TL512PC, "Tx512Byte"),
  204. + MIB_DESC(1, MT7621_STATS_TL1024PC, "Tx1024Byte"),
  205. + MIB_DESC(2, MT7621_STATS_TOC, "TxByte"),
  206. + MIB_DESC(1, MT7621_STATS_RDPC, "RxDrop"),
  207. + MIB_DESC(1, MT7621_STATS_RFPC, "RxFiltered"),
  208. + MIB_DESC(1, MT7621_STATS_RUPC, "RxUni"),
  209. + MIB_DESC(1, MT7621_STATS_RMPC, "RxMulti"),
  210. + MIB_DESC(1, MT7621_STATS_RBPC, "RxBroad"),
  211. + MIB_DESC(1, MT7621_STATS_RAEPC, "RxAlignErr"),
  212. + MIB_DESC(1, MT7621_STATS_RCEPC, "RxCRC"),
  213. + MIB_DESC(1, MT7621_STATS_RUSPC, "RxUnderSize"),
  214. + MIB_DESC(1, MT7621_STATS_RFEPC, "RxFragment"),
  215. + MIB_DESC(1, MT7621_STATS_ROSPC, "RxOverSize"),
  216. + MIB_DESC(1, MT7621_STATS_RJEPC, "RxJabber"),
  217. + MIB_DESC(1, MT7621_STATS_RPPC, "RxPause"),
  218. + MIB_DESC(1, MT7621_STATS_RL64PC, "Rx64Byte"),
  219. + MIB_DESC(1, MT7621_STATS_RL65PC, "Rx65Byte"),
  220. + MIB_DESC(1, MT7621_STATS_RL128PC, "Rx128Byte"),
  221. + MIB_DESC(1, MT7621_STATS_RL256PC, "Rx256Byte"),
  222. + MIB_DESC(1, MT7621_STATS_RL512PC, "Rx512Byte"),
  223. + MIB_DESC(1, MT7621_STATS_RL1024PC, "Rx1024Byte"),
  224. + MIB_DESC(2, MT7621_STATS_ROC, "RxByte"),
  225. + MIB_DESC(1, MT7621_STATS_RDPC_CTRL, "RxCtrlDrop"),
  226. + MIB_DESC(1, MT7621_STATS_RDPC_ING, "RxIngDrop"),
  227. + MIB_DESC(1, MT7621_STATS_RDPC_ARL, "RxARLDrop")
  228. +};
  229. +
  230. +enum {
  231. + /* Global attributes. */
  232. + MT7530_ATTR_ENABLE_VLAN,
  233. +};
  234. +
  235. +struct mt7530_port_entry {
  236. + u16 pvid;
  237. +};
  238. +
  239. +struct mt7530_vlan_entry {
  240. + u16 vid;
  241. + u8 member;
  242. + u8 etags;
  243. +};
  244. +
  245. +struct mt7530_priv {
  246. + void __iomem *base;
  247. + struct mii_bus *bus;
  248. + struct switch_dev swdev;
  249. +
  250. + bool global_vlan_enable;
  251. + struct mt7530_vlan_entry vlan_entries[MT7530_NUM_VLANS];
  252. + struct mt7530_port_entry port_entries[MT7530_NUM_PORTS];
  253. +};
  254. +
  255. +struct mt7530_mapping {
  256. + char *name;
  257. + u16 pvids[MT7530_NUM_PORTS];
  258. + u8 members[MT7530_NUM_VLANS];
  259. + u8 etags[MT7530_NUM_VLANS];
  260. + u16 vids[MT7530_NUM_VLANS];
  261. +} mt7530_defaults[] = {
  262. + {
  263. + .name = "llllw",
  264. + .pvids = { 1, 1, 1, 1, 2, 1, 1 },
  265. + .members = { 0, 0x6f, 0x50 },
  266. + .etags = { 0, 0x40, 0x40 },
  267. + .vids = { 0, 1, 2 },
  268. + }, {
  269. + .name = "wllll",
  270. + .pvids = { 2, 1, 1, 1, 1, 1, 1 },
  271. + .members = { 0, 0x7e, 0x41 },
  272. + .etags = { 0, 0x40, 0x40 },
  273. + .vids = { 0, 1, 2 },
  274. + },
  275. +};
  276. +
  277. +struct mt7530_mapping*
  278. +mt7530_find_mapping(struct device_node *np)
  279. +{
  280. + const char *map;
  281. + int i;
  282. +
  283. + if (of_property_read_string(np, "mediatek,portmap", &map))
  284. + return NULL;
  285. +
  286. + for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
  287. + if (!strcmp(map, mt7530_defaults[i].name))
  288. + return &mt7530_defaults[i];
  289. +
  290. + return NULL;
  291. +}
  292. +
  293. +static void
  294. +mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
  295. +{
  296. + int i = 0;
  297. +
  298. + for (i = 0; i < MT7530_NUM_PORTS; i++)
  299. + mt7530->port_entries[i].pvid = map->pvids[i];
  300. +
  301. + for (i = 0; i < MT7530_NUM_VLANS; i++) {
  302. + mt7530->vlan_entries[i].member = map->members[i];
  303. + mt7530->vlan_entries[i].etags = map->etags[i];
  304. + mt7530->vlan_entries[i].vid = map->vids[i];
  305. + }
  306. +}
  307. +
  308. +static int
  309. +mt7530_reset_switch(struct switch_dev *dev)
  310. +{
  311. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  312. + int i;
  313. +
  314. + memset(priv->port_entries, 0, sizeof(priv->port_entries));
  315. + memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
  316. +
  317. + /* set default vid of each vlan to the same number of vlan, so the vid
  318. + * won't need be set explicitly.
  319. + */
  320. + for (i = 0; i < MT7530_NUM_VLANS; i++) {
  321. + priv->vlan_entries[i].vid = i;
  322. + }
  323. +
  324. + return 0;
  325. +}
  326. +
  327. +static int
  328. +mt7530_get_vlan_enable(struct switch_dev *dev,
  329. + const struct switch_attr *attr,
  330. + struct switch_val *val)
  331. +{
  332. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  333. +
  334. + val->value.i = priv->global_vlan_enable;
  335. +
  336. + return 0;
  337. +}
  338. +
  339. +static int
  340. +mt7530_set_vlan_enable(struct switch_dev *dev,
  341. + const struct switch_attr *attr,
  342. + struct switch_val *val)
  343. +{
  344. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  345. +
  346. + priv->global_vlan_enable = val->value.i != 0;
  347. +
  348. + return 0;
  349. +}
  350. +
  351. +static u32
  352. +mt7530_r32(struct mt7530_priv *priv, u32 reg)
  353. +{
  354. + u32 val;
  355. + if (priv->bus) {
  356. + u16 high, low;
  357. +
  358. + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
  359. + low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
  360. + high = mdiobus_read(priv->bus, 0x1f, 0x10);
  361. +
  362. + return (high << 16) | (low & 0xffff);
  363. + }
  364. +
  365. + val = ioread32(priv->base + reg);
  366. + pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
  367. +
  368. + return val;
  369. +}
  370. +
  371. +static void
  372. +mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
  373. +{
  374. + if (priv->bus) {
  375. + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
  376. + mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
  377. + mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
  378. + return;
  379. + }
  380. +
  381. + pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
  382. + iowrite32(val, priv->base + reg);
  383. +}
  384. +
  385. +static void
  386. +mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
  387. +{
  388. + int i;
  389. +
  390. + mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
  391. +
  392. + for (i = 0; i < 20; i++) {
  393. + u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
  394. +
  395. + if ((val & BIT(31)) == 0)
  396. + break;
  397. +
  398. + udelay(1000);
  399. + }
  400. + if (i == 20)
  401. + printk("mt7530: vtcr timeout\n");
  402. +}
  403. +
  404. +static int
  405. +mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
  406. +{
  407. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  408. +
  409. + if (port >= MT7530_NUM_PORTS)
  410. + return -EINVAL;
  411. +
  412. + *val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
  413. + *val &= 0xfff;
  414. +
  415. + return 0;
  416. +}
  417. +
  418. +static int
  419. +mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
  420. +{
  421. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  422. +
  423. + if (port >= MT7530_NUM_PORTS)
  424. + return -EINVAL;
  425. +
  426. + if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
  427. + return -EINVAL;
  428. +
  429. + priv->port_entries[port].pvid = pvid;
  430. +
  431. + return 0;
  432. +}
  433. +
  434. +static int
  435. +mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
  436. +{
  437. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  438. + u32 member;
  439. + u32 etags;
  440. + int i;
  441. +
  442. + val->len = 0;
  443. +
  444. + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
  445. + return -EINVAL;
  446. +
  447. + mt7530_vtcr(priv, 0, val->port_vlan);
  448. +
  449. + member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
  450. + member >>= 16;
  451. + member &= 0xff;
  452. +
  453. + etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
  454. +
  455. + for (i = 0; i < MT7530_NUM_PORTS; i++) {
  456. + struct switch_port *p;
  457. + int etag;
  458. +
  459. + if (!(member & BIT(i)))
  460. + continue;
  461. +
  462. + p = &val->value.ports[val->len++];
  463. + p->id = i;
  464. +
  465. + etag = (etags >> (i * 2)) & 0x3;
  466. +
  467. + if (etag == ETAG_CTRL_TAG)
  468. + p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
  469. + else if (etag != ETAG_CTRL_UNTAG)
  470. + printk("vlan egress tag control neither untag nor tag.\n");
  471. + }
  472. +
  473. + return 0;
  474. +}
  475. +
  476. +static int
  477. +mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
  478. +{
  479. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  480. + u8 member = 0;
  481. + u8 etags = 0;
  482. + int i;
  483. +
  484. + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
  485. + val->len > MT7530_NUM_PORTS)
  486. + return -EINVAL;
  487. +
  488. + for (i = 0; i < val->len; i++) {
  489. + struct switch_port *p = &val->value.ports[i];
  490. +
  491. + if (p->id >= MT7530_NUM_PORTS)
  492. + return -EINVAL;
  493. +
  494. + member |= BIT(p->id);
  495. +
  496. + if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
  497. + etags |= BIT(p->id);
  498. + }
  499. + priv->vlan_entries[val->port_vlan].member = member;
  500. + priv->vlan_entries[val->port_vlan].etags = etags;
  501. +
  502. + return 0;
  503. +}
  504. +
  505. +static int
  506. +mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
  507. + struct switch_val *val)
  508. +{
  509. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  510. + int vlan;
  511. + u16 vid;
  512. +
  513. + vlan = val->port_vlan;
  514. + vid = (u16)val->value.i;
  515. +
  516. + if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
  517. + return -EINVAL;
  518. +
  519. + if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
  520. + return -EINVAL;
  521. +
  522. + priv->vlan_entries[vlan].vid = vid;
  523. + return 0;
  524. +}
  525. +
  526. +static int
  527. +mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
  528. + struct switch_val *val)
  529. +{
  530. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  531. + u32 vid;
  532. + int vlan;
  533. +
  534. + vlan = val->port_vlan;
  535. +
  536. + vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
  537. + if (vlan & 1)
  538. + vid = vid >> 12;
  539. + vid &= 0xfff;
  540. +
  541. + val->value.i = vid;
  542. + return 0;
  543. +}
  544. +
  545. +static int
  546. +mt7530_apply_config(struct switch_dev *dev)
  547. +{
  548. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  549. + int i, j;
  550. + u8 tag_ports;
  551. + u8 untag_ports;
  552. +
  553. + if (!priv->global_vlan_enable) {
  554. + for (i = 0; i < MT7530_NUM_PORTS; i++)
  555. + mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00400000);
  556. +
  557. + mt7530_w32(priv, REG_ESW_PORT_PCR(MT7530_CPU_PORT), 0x00ff0000);
  558. +
  559. + for (i = 0; i < MT7530_NUM_PORTS; i++)
  560. + mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x810000c0);
  561. +
  562. + return 0;
  563. + }
  564. +
  565. + /* set all ports as security mode */
  566. + for (i = 0; i < MT7530_NUM_PORTS; i++)
  567. + mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
  568. +
  569. + /* check if a port is used in tag/untag vlan egress mode */
  570. + tag_ports = 0;
  571. + untag_ports = 0;
  572. +
  573. + for (i = 0; i < MT7530_NUM_VLANS; i++) {
  574. + u8 member = priv->vlan_entries[i].member;
  575. + u8 etags = priv->vlan_entries[i].etags;
  576. +
  577. + if (!member)
  578. + continue;
  579. +
  580. + for (j = 0; j < MT7530_NUM_PORTS; j++) {
  581. + if (!(member & BIT(j)))
  582. + continue;
  583. +
  584. + if (etags & BIT(j))
  585. + tag_ports |= 1u << j;
  586. + else
  587. + untag_ports |= 1u << j;
  588. + }
  589. + }
  590. +
  591. + /* set all untag-only ports as transparent and the rest as user port */
  592. + for (i = 0; i < MT7530_NUM_PORTS; i++) {
  593. + u32 pvc_mode = 0x81000000;
  594. +
  595. + if (untag_ports & BIT(i) && !(tag_ports & BIT(i)))
  596. + pvc_mode = 0x810000c0;
  597. +
  598. + mt7530_w32(priv, REG_ESW_PORT_PVC(i), pvc_mode);
  599. + }
  600. +
  601. + for (i = 0; i < MT7530_NUM_VLANS; i++) {
  602. + u16 vid = priv->vlan_entries[i].vid;
  603. + u8 member = priv->vlan_entries[i].member;
  604. + u8 etags = priv->vlan_entries[i].etags;
  605. + u32 val;
  606. +
  607. + /* vid of vlan */
  608. + val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(i));
  609. + if (i % 2 == 0) {
  610. + val &= 0xfff000;
  611. + val |= vid;
  612. + } else {
  613. + val &= 0xfff;
  614. + val |= (vid << 12);
  615. + }
  616. + mt7530_w32(priv, REG_ESW_VLAN_VTIM(i), val);
  617. +
  618. + /* vlan port membership */
  619. + if (member)
  620. + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
  621. + REG_ESW_VLAN_VAWD1_VTAG_EN | (member << 16) |
  622. + REG_ESW_VLAN_VAWD1_VALID);
  623. + else
  624. + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
  625. +
  626. + /* egress mode */
  627. + val = 0;
  628. + for (j = 0; j < MT7530_NUM_PORTS; j++) {
  629. + if (etags & BIT(j))
  630. + val |= ETAG_CTRL_TAG << (j * 2);
  631. + else
  632. + val |= ETAG_CTRL_UNTAG << (j * 2);
  633. + }
  634. + mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
  635. +
  636. + /* write to vlan table */
  637. + mt7530_vtcr(priv, 1, i);
  638. + }
  639. +
  640. + /* Port Default PVID */
  641. + for (i = 0; i < MT7530_NUM_PORTS; i++) {
  642. + u32 val;
  643. + val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
  644. + val &= ~0xfff;
  645. + val |= priv->port_entries[i].pvid;
  646. + mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
  647. + }
  648. +
  649. + return 0;
  650. +}
  651. +
  652. +static int
  653. +mt7530_get_port_link(struct switch_dev *dev, int port,
  654. + struct switch_port_link *link)
  655. +{
  656. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  657. + u32 speed, pmsr;
  658. +
  659. + if (port < 0 || port >= MT7530_NUM_PORTS)
  660. + return -EINVAL;
  661. +
  662. + pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
  663. +
  664. + link->link = pmsr & 1;
  665. + link->duplex = (pmsr >> 1) & 1;
  666. + speed = (pmsr >> 2) & 3;
  667. +
  668. + switch (speed) {
  669. + case 0:
  670. + link->speed = SWITCH_PORT_SPEED_10;
  671. + break;
  672. + case 1:
  673. + link->speed = SWITCH_PORT_SPEED_100;
  674. + break;
  675. + case 2:
  676. + case 3: /* forced gige speed can be 2 or 3 */
  677. + link->speed = SWITCH_PORT_SPEED_1000;
  678. + break;
  679. + default:
  680. + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
  681. + break;
  682. + }
  683. +
  684. + return 0;
  685. +}
  686. +
  687. +static u64 get_mib_counter(struct mt7530_priv *priv, int i, int port)
  688. +{
  689. + unsigned int port_base;
  690. + u64 lo;
  691. +
  692. + port_base = MT7621_MIB_COUNTER_BASE +
  693. + MT7621_MIB_COUNTER_PORT_OFFSET * port;
  694. +
  695. + lo = mt7530_r32(priv, port_base + mt7621_mibs[i].offset);
  696. + if (mt7621_mibs[i].size == 2) {
  697. + u64 hi;
  698. +
  699. + hi = mt7530_r32(priv, port_base + mt7621_mibs[i].offset + 4);
  700. + lo |= hi << 32;
  701. + }
  702. +
  703. + return lo;
  704. +}
  705. +
  706. +static int mt7621_sw_get_port_mib(struct switch_dev *dev,
  707. + const struct switch_attr *attr,
  708. + struct switch_val *val)
  709. +{
  710. + static char buf[4096];
  711. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  712. + int i, len = 0;
  713. +
  714. + if (val->port_vlan >= MT7530_NUM_PORTS)
  715. + return -EINVAL;
  716. +
  717. + len += snprintf(buf + len, sizeof(buf) - len,
  718. + "Port %d MIB counters\n", val->port_vlan);
  719. +
  720. + for (i = 0; i < ARRAY_SIZE(mt7621_mibs); ++i) {
  721. + u64 counter;
  722. + len += snprintf(buf + len, sizeof(buf) - len,
  723. + "%-11s: ", mt7621_mibs[i].name);
  724. + counter = get_mib_counter(priv, i, val->port_vlan);
  725. + len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
  726. + counter);
  727. + }
  728. +
  729. + val->value.s = buf;
  730. + val->len = len;
  731. + return 0;
  732. +}
  733. +
  734. +static u64 get_mib_counter_7620(struct mt7530_priv *priv, int i)
  735. +{
  736. + return mt7530_r32(priv, MT7620_MIB_COUNTER_BASE + mt7620_mibs[i].offset);
  737. +}
  738. +
  739. +static u64 get_mib_counter_port_7620(struct mt7530_priv *priv, int i, int port)
  740. +{
  741. + return mt7530_r32(priv,
  742. + MT7620_MIB_COUNTER_BASE_PORT +
  743. + (MT7620_MIB_COUNTER_PORT_OFFSET * port) +
  744. + mt7620_port_mibs[i].offset);
  745. +}
  746. +
  747. +static int mt7530_sw_get_mib(struct switch_dev *dev,
  748. + const struct switch_attr *attr,
  749. + struct switch_val *val)
  750. +{
  751. + static char buf[4096];
  752. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  753. + int i, len = 0;
  754. +
  755. + len += snprintf(buf + len, sizeof(buf) - len, "Switch MIB counters\n");
  756. +
  757. + for (i = 0; i < ARRAY_SIZE(mt7620_mibs); ++i) {
  758. + u64 counter;
  759. + len += snprintf(buf + len, sizeof(buf) - len,
  760. + "%-11s: ", mt7620_mibs[i].name);
  761. + counter = get_mib_counter_7620(priv, i);
  762. + len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
  763. + counter);
  764. + }
  765. +
  766. + val->value.s = buf;
  767. + val->len = len;
  768. + return 0;
  769. +}
  770. +
  771. +static int mt7530_sw_get_port_mib(struct switch_dev *dev,
  772. + const struct switch_attr *attr,
  773. + struct switch_val *val)
  774. +{
  775. + static char buf[4096];
  776. + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
  777. + int i, len = 0;
  778. +
  779. + if (val->port_vlan >= MT7530_NUM_PORTS)
  780. + return -EINVAL;
  781. +
  782. + len += snprintf(buf + len, sizeof(buf) - len,
  783. + "Port %d MIB counters\n", val->port_vlan);
  784. +
  785. + for (i = 0; i < ARRAY_SIZE(mt7620_port_mibs); ++i) {
  786. + u64 counter;
  787. + len += snprintf(buf + len, sizeof(buf) - len,
  788. + "%-11s: ", mt7620_port_mibs[i].name);
  789. + counter = get_mib_counter_port_7620(priv, i, val->port_vlan);
  790. + len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
  791. + counter);
  792. + }
  793. +
  794. + val->value.s = buf;
  795. + val->len = len;
  796. + return 0;
  797. +}
  798. +
  799. +static const struct switch_attr mt7530_global[] = {
  800. + {
  801. + .type = SWITCH_TYPE_INT,
  802. + .name = "enable_vlan",
  803. + .description = "VLAN mode (1:enabled)",
  804. + .max = 1,
  805. + .id = MT7530_ATTR_ENABLE_VLAN,
  806. + .get = mt7530_get_vlan_enable,
  807. + .set = mt7530_set_vlan_enable,
  808. + }, {
  809. + .type = SWITCH_TYPE_STRING,
  810. + .name = "mib",
  811. + .description = "Get MIB counters for switch",
  812. + .get = mt7530_sw_get_mib,
  813. + .set = NULL,
  814. + },
  815. +};
  816. +
  817. +static const struct switch_attr mt7621_port[] = {
  818. + {
  819. + .type = SWITCH_TYPE_STRING,
  820. + .name = "mib",
  821. + .description = "Get MIB counters for port",
  822. + .get = mt7621_sw_get_port_mib,
  823. + .set = NULL,
  824. + },
  825. +};
  826. +
  827. +static const struct switch_attr mt7530_port[] = {
  828. + {
  829. + .type = SWITCH_TYPE_STRING,
  830. + .name = "mib",
  831. + .description = "Get MIB counters for port",
  832. + .get = mt7530_sw_get_port_mib,
  833. + .set = NULL,
  834. + },
  835. +};
  836. +
  837. +static const struct switch_attr mt7530_vlan[] = {
  838. + {
  839. + .type = SWITCH_TYPE_INT,
  840. + .name = "vid",
  841. + .description = "VLAN ID (0-4094)",
  842. + .set = mt7530_set_vid,
  843. + .get = mt7530_get_vid,
  844. + .max = 4094,
  845. + },
  846. +};
  847. +
  848. +static const struct switch_dev_ops mt7621_ops = {
  849. + .attr_global = {
  850. + .attr = mt7530_global,
  851. + .n_attr = ARRAY_SIZE(mt7530_global),
  852. + },
  853. + .attr_port = {
  854. + .attr = mt7621_port,
  855. + .n_attr = ARRAY_SIZE(mt7621_port),
  856. + },
  857. + .attr_vlan = {
  858. + .attr = mt7530_vlan,
  859. + .n_attr = ARRAY_SIZE(mt7530_vlan),
  860. + },
  861. + .get_vlan_ports = mt7530_get_vlan_ports,
  862. + .set_vlan_ports = mt7530_set_vlan_ports,
  863. + .get_port_pvid = mt7530_get_port_pvid,
  864. + .set_port_pvid = mt7530_set_port_pvid,
  865. + .get_port_link = mt7530_get_port_link,
  866. + .apply_config = mt7530_apply_config,
  867. + .reset_switch = mt7530_reset_switch,
  868. +};
  869. +
  870. +static const struct switch_dev_ops mt7530_ops = {
  871. + .attr_global = {
  872. + .attr = mt7530_global,
  873. + .n_attr = ARRAY_SIZE(mt7530_global),
  874. + },
  875. + .attr_port = {
  876. + .attr = mt7530_port,
  877. + .n_attr = ARRAY_SIZE(mt7530_port),
  878. + },
  879. + .attr_vlan = {
  880. + .attr = mt7530_vlan,
  881. + .n_attr = ARRAY_SIZE(mt7530_vlan),
  882. + },
  883. + .get_vlan_ports = mt7530_get_vlan_ports,
  884. + .set_vlan_ports = mt7530_set_vlan_ports,
  885. + .get_port_pvid = mt7530_get_port_pvid,
  886. + .set_port_pvid = mt7530_set_port_pvid,
  887. + .get_port_link = mt7530_get_port_link,
  888. + .apply_config = mt7530_apply_config,
  889. + .reset_switch = mt7530_reset_switch,
  890. +};
  891. +
  892. +int
  893. +mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
  894. +{
  895. + struct switch_dev *swdev;
  896. + struct mt7530_priv *mt7530;
  897. + struct mt7530_mapping *map;
  898. + int ret;
  899. +
  900. + mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
  901. + if (!mt7530)
  902. + return -ENOMEM;
  903. +
  904. + mt7530->base = base;
  905. + mt7530->bus = bus;
  906. + mt7530->global_vlan_enable = vlan;
  907. +
  908. + swdev = &mt7530->swdev;
  909. + if (bus) {
  910. + swdev->alias = "mt7530";
  911. + swdev->name = "mt7530";
  912. + } else if (IS_ENABLED(CONFIG_SOC_MT7621)) {
  913. + swdev->alias = "mt7621";
  914. + swdev->name = "mt7621";
  915. + } else {
  916. + swdev->alias = "mt7620";
  917. + swdev->name = "mt7620";
  918. + }
  919. + swdev->cpu_port = MT7530_CPU_PORT;
  920. + swdev->ports = MT7530_NUM_PORTS;
  921. + swdev->vlans = MT7530_NUM_VLANS;
  922. + if (IS_ENABLED(CONFIG_SOC_MT7621))
  923. + swdev->ops = &mt7621_ops;
  924. + else
  925. + swdev->ops = &mt7530_ops;
  926. +
  927. + ret = register_switch(swdev, NULL);
  928. + if (ret) {
  929. + dev_err(dev, "failed to register mt7530\n");
  930. + return ret;
  931. + }
  932. +
  933. +
  934. + map = mt7530_find_mapping(dev->of_node);
  935. + if (map)
  936. + mt7530_apply_mapping(mt7530, map);
  937. + mt7530_apply_config(swdev);
  938. +
  939. + /* magic vodoo */
  940. + if (!IS_ENABLED(CONFIG_SOC_MT7621) && bus && mt7530_r32(mt7530, REG_HWTRAP) != 0x1117edf) {
  941. + dev_info(dev, "fixing up MHWTRAP register - bootloader probably played with it\n");
  942. + mt7530_w32(mt7530, REG_HWTRAP, 0x1117edf);
  943. + }
  944. + dev_info(dev, "loaded %s driver\n", swdev->name);
  945. +
  946. + return 0;
  947. +}
  948. --- /dev/null
  949. +++ b/drivers/net/ethernet/mediatek/mt7530.h
  950. @@ -0,0 +1,186 @@
  951. +/*
  952. + * This program is free software; you can redistribute it and/or
  953. + * modify it under the terms of the GNU General Public License
  954. + * as published by the Free Software Foundation; either version 2
  955. + * of the License, or (at your option) any later version.
  956. + *
  957. + * This program is distributed in the hope that it will be useful,
  958. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  959. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  960. + * GNU General Public License for more details.
  961. + *
  962. + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  963. + * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
  964. + */
  965. +
  966. +#ifndef _MT7530_H__
  967. +#define _MT7530_H__
  968. +
  969. +#define MT7620_MIB_COUNTER_BASE_PORT 0x4000
  970. +#define MT7620_MIB_COUNTER_PORT_OFFSET 0x100
  971. +#define MT7620_MIB_COUNTER_BASE 0x1010
  972. +
  973. +/* PPE Accounting Group #0 Byte Counter */
  974. +#define MT7620_MIB_STATS_PPE_AC_BCNT0 0x000
  975. +
  976. +/* PPE Accounting Group #0 Packet Counter */
  977. +#define MT7620_MIB_STATS_PPE_AC_PCNT0 0x004
  978. +
  979. +/* PPE Accounting Group #63 Byte Counter */
  980. +#define MT7620_MIB_STATS_PPE_AC_BCNT63 0x1F8
  981. +
  982. +/* PPE Accounting Group #63 Packet Counter */
  983. +#define MT7620_MIB_STATS_PPE_AC_PCNT63 0x1FC
  984. +
  985. +/* PPE Meter Group #0 */
  986. +#define MT7620_MIB_STATS_PPE_MTR_CNT0 0x200
  987. +
  988. +/* PPE Meter Group #63 */
  989. +#define MT7620_MIB_STATS_PPE_MTR_CNT63 0x2FC
  990. +
  991. +/* Transmit good byte count for CPU GDM */
  992. +#define MT7620_MIB_STATS_GDM1_TX_GBCNT 0x300
  993. +
  994. +/* Transmit good packet count for CPU GDM (exclude flow control frames) */
  995. +#define MT7620_MIB_STATS_GDM1_TX_GPCNT 0x304
  996. +
  997. +/* Transmit abort count for CPU GDM */
  998. +#define MT7620_MIB_STATS_GDM1_TX_SKIPCNT 0x308
  999. +
  1000. +/* Transmit collision count for CPU GDM */
  1001. +#define MT7620_MIB_STATS_GDM1_TX_COLCNT 0x30C
  1002. +
  1003. +/* Received good byte count for CPU GDM */
  1004. +#define MT7620_MIB_STATS_GDM1_RX_GBCNT1 0x320
  1005. +
  1006. +/* Received good packet count for CPU GDM (exclude flow control frame) */
  1007. +#define MT7620_MIB_STATS_GDM1_RX_GPCNT1 0x324
  1008. +
  1009. +/* Received overflow error packet count for CPU GDM */
  1010. +#define MT7620_MIB_STATS_GDM1_RX_OERCNT 0x328
  1011. +
  1012. +/* Received FCS error packet count for CPU GDM */
  1013. +#define MT7620_MIB_STATS_GDM1_RX_FERCNT 0x32C
  1014. +
  1015. +/* Received too short error packet count for CPU GDM */
  1016. +#define MT7620_MIB_STATS_GDM1_RX_SERCNT 0x330
  1017. +
  1018. +/* Received too long error packet count for CPU GDM */
  1019. +#define MT7620_MIB_STATS_GDM1_RX_LERCNT 0x334
  1020. +
  1021. +/* Received IP/TCP/UDP checksum error packet count for CPU GDM */
  1022. +#define MT7620_MIB_STATS_GDM1_RX_CERCNT 0x338
  1023. +
  1024. +/* Received flow control pkt count for CPU GDM */
  1025. +#define MT7620_MIB_STATS_GDM1_RX_FCCNT 0x33C
  1026. +
  1027. +/* Transmit good byte count for PPE GDM */
  1028. +#define MT7620_MIB_STATS_GDM2_TX_GBCNT 0x340
  1029. +
  1030. +/* Transmit good packet count for PPE GDM (exclude flow control frames) */
  1031. +#define MT7620_MIB_STATS_GDM2_TX_GPCNT 0x344
  1032. +
  1033. +/* Transmit abort count for PPE GDM */
  1034. +#define MT7620_MIB_STATS_GDM2_TX_SKIPCNT 0x348
  1035. +
  1036. +/* Transmit collision count for PPE GDM */
  1037. +#define MT7620_MIB_STATS_GDM2_TX_COLCNT 0x34C
  1038. +
  1039. +/* Received good byte count for PPE GDM */
  1040. +#define MT7620_MIB_STATS_GDM2_RX_GBCNT 0x360
  1041. +
  1042. +/* Received good packet count for PPE GDM (exclude flow control frame) */
  1043. +#define MT7620_MIB_STATS_GDM2_RX_GPCNT 0x364
  1044. +
  1045. +/* Received overflow error packet count for PPE GDM */
  1046. +#define MT7620_MIB_STATS_GDM2_RX_OERCNT 0x368
  1047. +
  1048. +/* Received FCS error packet count for PPE GDM */
  1049. +#define MT7620_MIB_STATS_GDM2_RX_FERCNT 0x36C
  1050. +
  1051. +/* Received too short error packet count for PPE GDM */
  1052. +#define MT7620_MIB_STATS_GDM2_RX_SERCNT 0x370
  1053. +
  1054. +/* Received too long error packet count for PPE GDM */
  1055. +#define MT7620_MIB_STATS_GDM2_RX_LERCNT 0x374
  1056. +
  1057. +/* Received IP/TCP/UDP checksum error packet count for PPE GDM */
  1058. +#define MT7620_MIB_STATS_GDM2_RX_CERCNT 0x378
  1059. +
  1060. +/* Received flow control pkt count for PPE GDM */
  1061. +#define MT7620_MIB_STATS_GDM2_RX_FCCNT 0x37C
  1062. +
  1063. +/* Tx Packet Counter of Port n */
  1064. +#define MT7620_MIB_STATS_PORT_TGPCN 0x10
  1065. +
  1066. +/* Tx Bad Octet Counter of Port n */
  1067. +#define MT7620_MIB_STATS_PORT_TBOCN 0x14
  1068. +
  1069. +/* Tx Good Octet Counter of Port n */
  1070. +#define MT7620_MIB_STATS_PORT_TGOCN 0x18
  1071. +
  1072. +/* Tx Event Packet Counter of Port n */
  1073. +#define MT7620_MIB_STATS_PORT_TEPCN 0x1C
  1074. +
  1075. +/* Rx Packet Counter of Port n */
  1076. +#define MT7620_MIB_STATS_PORT_RGPCN 0x20
  1077. +
  1078. +/* Rx Bad Octet Counter of Port n */
  1079. +#define MT7620_MIB_STATS_PORT_RBOCN 0x24
  1080. +
  1081. +/* Rx Good Octet Counter of Port n */
  1082. +#define MT7620_MIB_STATS_PORT_RGOCN 0x28
  1083. +
  1084. +/* Rx Event Packet Counter of Port n */
  1085. +#define MT7620_MIB_STATS_PORT_REPC1N 0x2C
  1086. +
  1087. +/* Rx Event Packet Counter of Port n */
  1088. +#define MT7620_MIB_STATS_PORT_REPC2N 0x30
  1089. +
  1090. +#define MT7621_MIB_COUNTER_BASE 0x4000
  1091. +#define MT7621_MIB_COUNTER_PORT_OFFSET 0x100
  1092. +#define MT7621_STATS_TDPC 0x00
  1093. +#define MT7621_STATS_TCRC 0x04
  1094. +#define MT7621_STATS_TUPC 0x08
  1095. +#define MT7621_STATS_TMPC 0x0C
  1096. +#define MT7621_STATS_TBPC 0x10
  1097. +#define MT7621_STATS_TCEC 0x14
  1098. +#define MT7621_STATS_TSCEC 0x18
  1099. +#define MT7621_STATS_TMCEC 0x1C
  1100. +#define MT7621_STATS_TDEC 0x20
  1101. +#define MT7621_STATS_TLCEC 0x24
  1102. +#define MT7621_STATS_TXCEC 0x28
  1103. +#define MT7621_STATS_TPPC 0x2C
  1104. +#define MT7621_STATS_TL64PC 0x30
  1105. +#define MT7621_STATS_TL65PC 0x34
  1106. +#define MT7621_STATS_TL128PC 0x38
  1107. +#define MT7621_STATS_TL256PC 0x3C
  1108. +#define MT7621_STATS_TL512PC 0x40
  1109. +#define MT7621_STATS_TL1024PC 0x44
  1110. +#define MT7621_STATS_TOC 0x48
  1111. +#define MT7621_STATS_RDPC 0x60
  1112. +#define MT7621_STATS_RFPC 0x64
  1113. +#define MT7621_STATS_RUPC 0x68
  1114. +#define MT7621_STATS_RMPC 0x6C
  1115. +#define MT7621_STATS_RBPC 0x70
  1116. +#define MT7621_STATS_RAEPC 0x74
  1117. +#define MT7621_STATS_RCEPC 0x78
  1118. +#define MT7621_STATS_RUSPC 0x7C
  1119. +#define MT7621_STATS_RFEPC 0x80
  1120. +#define MT7621_STATS_ROSPC 0x84
  1121. +#define MT7621_STATS_RJEPC 0x88
  1122. +#define MT7621_STATS_RPPC 0x8C
  1123. +#define MT7621_STATS_RL64PC 0x90
  1124. +#define MT7621_STATS_RL65PC 0x94
  1125. +#define MT7621_STATS_RL128PC 0x98
  1126. +#define MT7621_STATS_RL256PC 0x9C
  1127. +#define MT7621_STATS_RL512PC 0xA0
  1128. +#define MT7621_STATS_RL1024PC 0xA4
  1129. +#define MT7621_STATS_ROC 0xA8
  1130. +#define MT7621_STATS_RDPC_CTRL 0xB0
  1131. +#define MT7621_STATS_RDPC_ING 0xB4
  1132. +#define MT7621_STATS_RDPC_ARL 0xB8
  1133. +
  1134. +int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);
  1135. +
  1136. +#endif
  1137. --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  1138. +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  1139. @@ -1291,8 +1291,13 @@ static int __init fe_init(struct net_dev
  1140. }
  1141. err = fe_hw_init(dev);
  1142. - if (!err)
  1143. - return 0;
  1144. + if (err)
  1145. + goto err_phy_disconnect;
  1146. +
  1147. + if ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config)
  1148. + priv->soc->switch_config(priv);
  1149. +
  1150. + return 0;
  1151. err_phy_disconnect:
  1152. if (priv->phy)
  1153. --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  1154. +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  1155. @@ -383,6 +383,7 @@ struct fe_soc_data {
  1156. int (*fwd_config)(struct fe_priv *priv);
  1157. void (*tx_dma)(struct fe_tx_dma *txd);
  1158. int (*switch_init)(struct fe_priv *priv);
  1159. + int (*switch_config)(struct fe_priv *priv);
  1160. void (*port_init)(struct fe_priv *priv, struct device_node *port);
  1161. int (*has_carrier)(struct fe_priv *priv);
  1162. int (*mdio_init)(struct fe_priv *priv);
  1163. --- a/drivers/net/ethernet/mediatek/soc_mt7620.c
  1164. +++ b/drivers/net/ethernet/mediatek/soc_mt7620.c
  1165. @@ -313,6 +313,7 @@ static struct fe_soc_data mt7620_data =
  1166. .fwd_config = mt7620_fwd_config,
  1167. .tx_dma = mt7620_tx_dma,
  1168. .switch_init = mtk_gsw_init,
  1169. + .switch_config = mt7620_gsw_config,
  1170. .port_init = mt7620_port_init,
  1171. .reg_table = mt7620_reg_table,
  1172. .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,