dev-eth.c 27 KB

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  1. /*
  2. * Atheros AR71xx SoC platform devices
  3. *
  4. * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
  5. * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
  6. * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  7. *
  8. * Parts of this file are based on Atheros 2.6.15 BSP
  9. * Parts of this file are based on Atheros 2.6.31 BSP
  10. *
  11. * This program is free software; you can redistribute it and/or modify it
  12. * under the terms of the GNU General Public License version 2 as published
  13. * by the Free Software Foundation.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/delay.h>
  18. #include <linux/etherdevice.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/serial_8250.h>
  21. #include <linux/clk.h>
  22. #include <linux/sizes.h>
  23. #include <asm/mach-ath79/ath79.h>
  24. #include <asm/mach-ath79/ar71xx_regs.h>
  25. #include <asm/mach-ath79/irq.h>
  26. #include "common.h"
  27. #include "dev-eth.h"
  28. unsigned char ath79_mac_base[ETH_ALEN] __initdata;
  29. static struct resource ath79_mdio0_resources[] = {
  30. {
  31. .name = "mdio_base",
  32. .flags = IORESOURCE_MEM,
  33. .start = AR71XX_GE0_BASE,
  34. .end = AR71XX_GE0_BASE + 0x200 - 1,
  35. }
  36. };
  37. struct ag71xx_mdio_platform_data ath79_mdio0_data;
  38. struct platform_device ath79_mdio0_device = {
  39. .name = "ag71xx-mdio",
  40. .id = 0,
  41. .resource = ath79_mdio0_resources,
  42. .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
  43. .dev = {
  44. .platform_data = &ath79_mdio0_data,
  45. },
  46. };
  47. static struct resource ath79_mdio1_resources[] = {
  48. {
  49. .name = "mdio_base",
  50. .flags = IORESOURCE_MEM,
  51. .start = AR71XX_GE1_BASE,
  52. .end = AR71XX_GE1_BASE + 0x200 - 1,
  53. }
  54. };
  55. struct ag71xx_mdio_platform_data ath79_mdio1_data;
  56. struct platform_device ath79_mdio1_device = {
  57. .name = "ag71xx-mdio",
  58. .id = 1,
  59. .resource = ath79_mdio1_resources,
  60. .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
  61. .dev = {
  62. .platform_data = &ath79_mdio1_data,
  63. },
  64. };
  65. static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
  66. {
  67. void __iomem *base;
  68. u32 t;
  69. base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  70. t = __raw_readl(base + cfg_reg);
  71. t &= ~(3 << shift);
  72. t |= (2 << shift);
  73. __raw_writel(t, base + cfg_reg);
  74. udelay(100);
  75. __raw_writel(pll_val, base + pll_reg);
  76. t |= (3 << shift);
  77. __raw_writel(t, base + cfg_reg);
  78. udelay(100);
  79. t &= ~(3 << shift);
  80. __raw_writel(t, base + cfg_reg);
  81. udelay(100);
  82. printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
  83. (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
  84. iounmap(base);
  85. }
  86. static void __init ath79_mii_ctrl_set_if(unsigned int reg,
  87. unsigned int mii_if)
  88. {
  89. void __iomem *base;
  90. u32 t;
  91. base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
  92. t = __raw_readl(base + reg);
  93. t &= ~(AR71XX_MII_CTRL_IF_MASK);
  94. t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
  95. __raw_writel(t, base + reg);
  96. iounmap(base);
  97. }
  98. static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
  99. {
  100. void __iomem *base;
  101. unsigned int mii_speed;
  102. u32 t;
  103. switch (speed) {
  104. case SPEED_10:
  105. mii_speed = AR71XX_MII_CTRL_SPEED_10;
  106. break;
  107. case SPEED_100:
  108. mii_speed = AR71XX_MII_CTRL_SPEED_100;
  109. break;
  110. case SPEED_1000:
  111. mii_speed = AR71XX_MII_CTRL_SPEED_1000;
  112. break;
  113. default:
  114. BUG();
  115. }
  116. base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
  117. t = __raw_readl(base + reg);
  118. t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
  119. t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
  120. __raw_writel(t, base + reg);
  121. iounmap(base);
  122. }
  123. static unsigned long ar934x_get_mdio_ref_clock(void)
  124. {
  125. void __iomem *base;
  126. unsigned long ret;
  127. u32 t;
  128. base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  129. ret = 0;
  130. t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
  131. if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
  132. ret = 100 * 1000 * 1000;
  133. } else {
  134. struct clk *clk;
  135. clk = clk_get(NULL, "ref");
  136. if (!IS_ERR(clk))
  137. ret = clk_get_rate(clk);
  138. }
  139. iounmap(base);
  140. return ret;
  141. }
  142. void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
  143. {
  144. struct platform_device *mdio_dev;
  145. struct ag71xx_mdio_platform_data *mdio_data;
  146. unsigned int max_id;
  147. if (ath79_soc == ATH79_SOC_AR9341 ||
  148. ath79_soc == ATH79_SOC_AR9342 ||
  149. ath79_soc == ATH79_SOC_AR9344 ||
  150. ath79_soc == ATH79_SOC_QCA9556 ||
  151. ath79_soc == ATH79_SOC_QCA9558 ||
  152. ath79_soc == ATH79_SOC_QCA956X)
  153. max_id = 1;
  154. else
  155. max_id = 0;
  156. if (id > max_id) {
  157. printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
  158. return;
  159. }
  160. switch (ath79_soc) {
  161. case ATH79_SOC_AR7241:
  162. case ATH79_SOC_AR9330:
  163. case ATH79_SOC_AR9331:
  164. case ATH79_SOC_QCA9533:
  165. case ATH79_SOC_TP9343:
  166. mdio_dev = &ath79_mdio1_device;
  167. mdio_data = &ath79_mdio1_data;
  168. break;
  169. case ATH79_SOC_AR9341:
  170. case ATH79_SOC_AR9342:
  171. case ATH79_SOC_AR9344:
  172. case ATH79_SOC_QCA9556:
  173. case ATH79_SOC_QCA9558:
  174. case ATH79_SOC_QCA956X:
  175. if (id == 0) {
  176. mdio_dev = &ath79_mdio0_device;
  177. mdio_data = &ath79_mdio0_data;
  178. } else {
  179. mdio_dev = &ath79_mdio1_device;
  180. mdio_data = &ath79_mdio1_data;
  181. }
  182. break;
  183. case ATH79_SOC_AR7242:
  184. ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
  185. AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
  186. AR71XX_ETH0_PLL_SHIFT);
  187. /* fall through */
  188. default:
  189. mdio_dev = &ath79_mdio0_device;
  190. mdio_data = &ath79_mdio0_data;
  191. break;
  192. }
  193. mdio_data->phy_mask = phy_mask;
  194. switch (ath79_soc) {
  195. case ATH79_SOC_AR7240:
  196. mdio_data->is_ar7240 = 1;
  197. /* fall through */
  198. case ATH79_SOC_AR7241:
  199. mdio_data->builtin_switch = 1;
  200. break;
  201. case ATH79_SOC_AR9330:
  202. mdio_data->is_ar9330 = 1;
  203. /* fall through */
  204. case ATH79_SOC_AR9331:
  205. mdio_data->builtin_switch = 1;
  206. break;
  207. case ATH79_SOC_AR9341:
  208. case ATH79_SOC_AR9342:
  209. case ATH79_SOC_AR9344:
  210. if (id == 1) {
  211. mdio_data->builtin_switch = 1;
  212. mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
  213. mdio_data->mdio_clock = 6250000;
  214. }
  215. mdio_data->is_ar934x = 1;
  216. break;
  217. case ATH79_SOC_QCA9533:
  218. case ATH79_SOC_TP9343:
  219. mdio_data->builtin_switch = 1;
  220. break;
  221. case ATH79_SOC_QCA9556:
  222. case ATH79_SOC_QCA9558:
  223. mdio_data->is_ar934x = 1;
  224. break;
  225. case ATH79_SOC_QCA956X:
  226. if (id == 1)
  227. mdio_data->builtin_switch = 1;
  228. mdio_data->is_ar934x = 1;
  229. break;
  230. default:
  231. break;
  232. }
  233. platform_device_register(mdio_dev);
  234. }
  235. struct ath79_eth_pll_data ath79_eth0_pll_data;
  236. struct ath79_eth_pll_data ath79_eth1_pll_data;
  237. static u32 ath79_get_eth_pll(unsigned int mac, int speed)
  238. {
  239. struct ath79_eth_pll_data *pll_data;
  240. u32 pll_val;
  241. switch (mac) {
  242. case 0:
  243. pll_data = &ath79_eth0_pll_data;
  244. break;
  245. case 1:
  246. pll_data = &ath79_eth1_pll_data;
  247. break;
  248. default:
  249. BUG();
  250. }
  251. switch (speed) {
  252. case SPEED_10:
  253. pll_val = pll_data->pll_10;
  254. break;
  255. case SPEED_100:
  256. pll_val = pll_data->pll_100;
  257. break;
  258. case SPEED_1000:
  259. pll_val = pll_data->pll_1000;
  260. break;
  261. default:
  262. BUG();
  263. }
  264. return pll_val;
  265. }
  266. static void ath79_set_speed_ge0(int speed)
  267. {
  268. u32 val = ath79_get_eth_pll(0, speed);
  269. ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
  270. val, AR71XX_ETH0_PLL_SHIFT);
  271. ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
  272. }
  273. static void ath79_set_speed_ge1(int speed)
  274. {
  275. u32 val = ath79_get_eth_pll(1, speed);
  276. ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
  277. val, AR71XX_ETH1_PLL_SHIFT);
  278. ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
  279. }
  280. static void ar7242_set_speed_ge0(int speed)
  281. {
  282. u32 val = ath79_get_eth_pll(0, speed);
  283. void __iomem *base;
  284. base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  285. __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
  286. iounmap(base);
  287. }
  288. static void ar91xx_set_speed_ge0(int speed)
  289. {
  290. u32 val = ath79_get_eth_pll(0, speed);
  291. ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
  292. val, AR913X_ETH0_PLL_SHIFT);
  293. ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
  294. }
  295. static void ar91xx_set_speed_ge1(int speed)
  296. {
  297. u32 val = ath79_get_eth_pll(1, speed);
  298. ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
  299. val, AR913X_ETH1_PLL_SHIFT);
  300. ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
  301. }
  302. static void ar934x_set_speed_ge0(int speed)
  303. {
  304. void __iomem *base;
  305. u32 val = ath79_get_eth_pll(0, speed);
  306. base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  307. __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
  308. iounmap(base);
  309. }
  310. static void qca955x_set_speed_xmii(int speed)
  311. {
  312. void __iomem *base;
  313. u32 val = ath79_get_eth_pll(0, speed);
  314. base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  315. __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
  316. iounmap(base);
  317. }
  318. static void qca955x_set_speed_sgmii(int speed)
  319. {
  320. void __iomem *base;
  321. u32 val = ath79_get_eth_pll(1, speed);
  322. base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  323. __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
  324. iounmap(base);
  325. }
  326. static void qca956x_set_speed_sgmii(int speed)
  327. {
  328. void __iomem *base;
  329. u32 val = ath79_get_eth_pll(0, speed);
  330. base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  331. __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
  332. iounmap(base);
  333. }
  334. static void ath79_set_speed_dummy(int speed)
  335. {
  336. }
  337. static void ath79_ddr_flush_ge0(void)
  338. {
  339. ath79_ddr_wb_flush(0);
  340. }
  341. static void ath79_ddr_flush_ge1(void)
  342. {
  343. ath79_ddr_wb_flush(1);
  344. }
  345. static struct resource ath79_eth0_resources[] = {
  346. {
  347. .name = "mac_base",
  348. .flags = IORESOURCE_MEM,
  349. .start = AR71XX_GE0_BASE,
  350. .end = AR71XX_GE0_BASE + 0x200 - 1,
  351. }, {
  352. .name = "mac_irq",
  353. .flags = IORESOURCE_IRQ,
  354. .start = ATH79_CPU_IRQ(4),
  355. .end = ATH79_CPU_IRQ(4),
  356. },
  357. };
  358. struct ag71xx_platform_data ath79_eth0_data = {
  359. .reset_bit = AR71XX_RESET_GE0_MAC,
  360. };
  361. struct platform_device ath79_eth0_device = {
  362. .name = "ag71xx",
  363. .id = 0,
  364. .resource = ath79_eth0_resources,
  365. .num_resources = ARRAY_SIZE(ath79_eth0_resources),
  366. .dev = {
  367. .platform_data = &ath79_eth0_data,
  368. },
  369. };
  370. static struct resource ath79_eth1_resources[] = {
  371. {
  372. .name = "mac_base",
  373. .flags = IORESOURCE_MEM,
  374. .start = AR71XX_GE1_BASE,
  375. .end = AR71XX_GE1_BASE + 0x200 - 1,
  376. }, {
  377. .name = "mac_irq",
  378. .flags = IORESOURCE_IRQ,
  379. .start = ATH79_CPU_IRQ(5),
  380. .end = ATH79_CPU_IRQ(5),
  381. },
  382. };
  383. struct ag71xx_platform_data ath79_eth1_data = {
  384. .reset_bit = AR71XX_RESET_GE1_MAC,
  385. };
  386. struct platform_device ath79_eth1_device = {
  387. .name = "ag71xx",
  388. .id = 1,
  389. .resource = ath79_eth1_resources,
  390. .num_resources = ARRAY_SIZE(ath79_eth1_resources),
  391. .dev = {
  392. .platform_data = &ath79_eth1_data,
  393. },
  394. };
  395. struct ag71xx_switch_platform_data ath79_switch_data;
  396. #define AR71XX_PLL_VAL_1000 0x00110000
  397. #define AR71XX_PLL_VAL_100 0x00001099
  398. #define AR71XX_PLL_VAL_10 0x00991099
  399. #define AR724X_PLL_VAL_1000 0x00110000
  400. #define AR724X_PLL_VAL_100 0x00001099
  401. #define AR724X_PLL_VAL_10 0x00991099
  402. #define AR7242_PLL_VAL_1000 0x16000000
  403. #define AR7242_PLL_VAL_100 0x00000101
  404. #define AR7242_PLL_VAL_10 0x00001616
  405. #define AR913X_PLL_VAL_1000 0x1a000000
  406. #define AR913X_PLL_VAL_100 0x13000a44
  407. #define AR913X_PLL_VAL_10 0x00441099
  408. #define AR933X_PLL_VAL_1000 0x00110000
  409. #define AR933X_PLL_VAL_100 0x00001099
  410. #define AR933X_PLL_VAL_10 0x00991099
  411. #define AR934X_PLL_VAL_1000 0x16000000
  412. #define AR934X_PLL_VAL_100 0x00000101
  413. #define AR934X_PLL_VAL_10 0x00001616
  414. #define QCA956X_PLL_VAL_1000 0x03000000
  415. #define QCA956X_PLL_VAL_100 0x00000101
  416. #define QCA956X_PLL_VAL_10 0x00001919
  417. static void __init ath79_init_eth_pll_data(unsigned int id)
  418. {
  419. struct ath79_eth_pll_data *pll_data;
  420. u32 pll_10, pll_100, pll_1000;
  421. switch (id) {
  422. case 0:
  423. pll_data = &ath79_eth0_pll_data;
  424. break;
  425. case 1:
  426. pll_data = &ath79_eth1_pll_data;
  427. break;
  428. default:
  429. BUG();
  430. }
  431. switch (ath79_soc) {
  432. case ATH79_SOC_AR7130:
  433. case ATH79_SOC_AR7141:
  434. case ATH79_SOC_AR7161:
  435. pll_10 = AR71XX_PLL_VAL_10;
  436. pll_100 = AR71XX_PLL_VAL_100;
  437. pll_1000 = AR71XX_PLL_VAL_1000;
  438. break;
  439. case ATH79_SOC_AR7240:
  440. case ATH79_SOC_AR7241:
  441. pll_10 = AR724X_PLL_VAL_10;
  442. pll_100 = AR724X_PLL_VAL_100;
  443. pll_1000 = AR724X_PLL_VAL_1000;
  444. break;
  445. case ATH79_SOC_AR7242:
  446. pll_10 = AR7242_PLL_VAL_10;
  447. pll_100 = AR7242_PLL_VAL_100;
  448. pll_1000 = AR7242_PLL_VAL_1000;
  449. break;
  450. case ATH79_SOC_AR9130:
  451. case ATH79_SOC_AR9132:
  452. pll_10 = AR913X_PLL_VAL_10;
  453. pll_100 = AR913X_PLL_VAL_100;
  454. pll_1000 = AR913X_PLL_VAL_1000;
  455. break;
  456. case ATH79_SOC_AR9330:
  457. case ATH79_SOC_AR9331:
  458. pll_10 = AR933X_PLL_VAL_10;
  459. pll_100 = AR933X_PLL_VAL_100;
  460. pll_1000 = AR933X_PLL_VAL_1000;
  461. break;
  462. case ATH79_SOC_AR9341:
  463. case ATH79_SOC_AR9342:
  464. case ATH79_SOC_AR9344:
  465. case ATH79_SOC_QCA9533:
  466. case ATH79_SOC_QCA9556:
  467. case ATH79_SOC_QCA9558:
  468. case ATH79_SOC_TP9343:
  469. pll_10 = AR934X_PLL_VAL_10;
  470. pll_100 = AR934X_PLL_VAL_100;
  471. pll_1000 = AR934X_PLL_VAL_1000;
  472. break;
  473. case ATH79_SOC_QCA956X:
  474. pll_10 = QCA956X_PLL_VAL_10;
  475. pll_100 = QCA956X_PLL_VAL_100;
  476. pll_1000 = QCA956X_PLL_VAL_1000;
  477. break;
  478. default:
  479. BUG();
  480. }
  481. if (!pll_data->pll_10)
  482. pll_data->pll_10 = pll_10;
  483. if (!pll_data->pll_100)
  484. pll_data->pll_100 = pll_100;
  485. if (!pll_data->pll_1000)
  486. pll_data->pll_1000 = pll_1000;
  487. }
  488. static int __init ath79_setup_phy_if_mode(unsigned int id,
  489. struct ag71xx_platform_data *pdata)
  490. {
  491. unsigned int mii_if;
  492. switch (id) {
  493. case 0:
  494. switch (ath79_soc) {
  495. case ATH79_SOC_AR7130:
  496. case ATH79_SOC_AR7141:
  497. case ATH79_SOC_AR7161:
  498. case ATH79_SOC_AR9130:
  499. case ATH79_SOC_AR9132:
  500. switch (pdata->phy_if_mode) {
  501. case PHY_INTERFACE_MODE_MII:
  502. mii_if = AR71XX_MII0_CTRL_IF_MII;
  503. break;
  504. case PHY_INTERFACE_MODE_GMII:
  505. mii_if = AR71XX_MII0_CTRL_IF_GMII;
  506. break;
  507. case PHY_INTERFACE_MODE_RGMII:
  508. mii_if = AR71XX_MII0_CTRL_IF_RGMII;
  509. break;
  510. case PHY_INTERFACE_MODE_RMII:
  511. mii_if = AR71XX_MII0_CTRL_IF_RMII;
  512. break;
  513. default:
  514. return -EINVAL;
  515. }
  516. ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
  517. break;
  518. case ATH79_SOC_AR7240:
  519. case ATH79_SOC_AR7241:
  520. case ATH79_SOC_AR9330:
  521. case ATH79_SOC_AR9331:
  522. case ATH79_SOC_QCA9533:
  523. case ATH79_SOC_TP9343:
  524. pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
  525. break;
  526. case ATH79_SOC_AR7242:
  527. /* FIXME */
  528. case ATH79_SOC_AR9341:
  529. case ATH79_SOC_AR9342:
  530. case ATH79_SOC_AR9344:
  531. switch (pdata->phy_if_mode) {
  532. case PHY_INTERFACE_MODE_MII:
  533. case PHY_INTERFACE_MODE_GMII:
  534. case PHY_INTERFACE_MODE_RGMII:
  535. case PHY_INTERFACE_MODE_RMII:
  536. break;
  537. default:
  538. return -EINVAL;
  539. }
  540. break;
  541. case ATH79_SOC_QCA9556:
  542. case ATH79_SOC_QCA9558:
  543. case ATH79_SOC_QCA956X:
  544. switch (pdata->phy_if_mode) {
  545. case PHY_INTERFACE_MODE_MII:
  546. case PHY_INTERFACE_MODE_RGMII:
  547. case PHY_INTERFACE_MODE_SGMII:
  548. break;
  549. default:
  550. return -EINVAL;
  551. }
  552. break;
  553. default:
  554. BUG();
  555. }
  556. break;
  557. case 1:
  558. switch (ath79_soc) {
  559. case ATH79_SOC_AR7130:
  560. case ATH79_SOC_AR7141:
  561. case ATH79_SOC_AR7161:
  562. case ATH79_SOC_AR9130:
  563. case ATH79_SOC_AR9132:
  564. switch (pdata->phy_if_mode) {
  565. case PHY_INTERFACE_MODE_RMII:
  566. mii_if = AR71XX_MII1_CTRL_IF_RMII;
  567. break;
  568. case PHY_INTERFACE_MODE_RGMII:
  569. mii_if = AR71XX_MII1_CTRL_IF_RGMII;
  570. break;
  571. default:
  572. return -EINVAL;
  573. }
  574. ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
  575. break;
  576. case ATH79_SOC_AR7240:
  577. case ATH79_SOC_AR7241:
  578. case ATH79_SOC_AR9330:
  579. case ATH79_SOC_AR9331:
  580. case ATH79_SOC_QCA956X:
  581. case ATH79_SOC_TP9343:
  582. pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
  583. break;
  584. case ATH79_SOC_AR7242:
  585. /* FIXME */
  586. case ATH79_SOC_AR9341:
  587. case ATH79_SOC_AR9342:
  588. case ATH79_SOC_AR9344:
  589. case ATH79_SOC_QCA9533:
  590. switch (pdata->phy_if_mode) {
  591. case PHY_INTERFACE_MODE_MII:
  592. case PHY_INTERFACE_MODE_GMII:
  593. break;
  594. default:
  595. return -EINVAL;
  596. }
  597. break;
  598. case ATH79_SOC_QCA9556:
  599. case ATH79_SOC_QCA9558:
  600. switch (pdata->phy_if_mode) {
  601. case PHY_INTERFACE_MODE_MII:
  602. case PHY_INTERFACE_MODE_RGMII:
  603. case PHY_INTERFACE_MODE_SGMII:
  604. break;
  605. default:
  606. return -EINVAL;
  607. }
  608. break;
  609. default:
  610. BUG();
  611. }
  612. break;
  613. }
  614. return 0;
  615. }
  616. void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
  617. {
  618. void __iomem *base;
  619. u32 t;
  620. base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
  621. t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
  622. t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
  623. if (mac)
  624. t |= AR933X_ETH_CFG_SW_PHY_SWAP;
  625. if (mdio)
  626. t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
  627. __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
  628. iounmap(base);
  629. }
  630. void __init ath79_setup_ar934x_eth_cfg(u32 mask)
  631. {
  632. void __iomem *base;
  633. u32 t;
  634. base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
  635. t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
  636. t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
  637. AR934X_ETH_CFG_MII_GMAC0 |
  638. AR934X_ETH_CFG_GMII_GMAC0 |
  639. AR934X_ETH_CFG_SW_ONLY_MODE |
  640. AR934X_ETH_CFG_SW_PHY_SWAP);
  641. t |= mask;
  642. __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
  643. /* flush write */
  644. __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
  645. iounmap(base);
  646. }
  647. void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
  648. unsigned int rxdv)
  649. {
  650. void __iomem *base;
  651. u32 t;
  652. rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK;
  653. rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK;
  654. base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
  655. t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
  656. t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
  657. AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
  658. t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
  659. rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
  660. __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
  661. /* flush write */
  662. __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
  663. iounmap(base);
  664. }
  665. void __init ath79_setup_qca955x_eth_cfg(u32 mask)
  666. {
  667. void __iomem *base;
  668. u32 t;
  669. base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
  670. t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
  671. t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
  672. t |= mask;
  673. __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
  674. iounmap(base);
  675. }
  676. static int ath79_eth_instance __initdata;
  677. void __init ath79_register_eth(unsigned int id)
  678. {
  679. struct platform_device *pdev;
  680. struct ag71xx_platform_data *pdata;
  681. int err;
  682. if (id > 1) {
  683. printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
  684. return;
  685. }
  686. ath79_init_eth_pll_data(id);
  687. if (id == 0)
  688. pdev = &ath79_eth0_device;
  689. else
  690. pdev = &ath79_eth1_device;
  691. pdata = pdev->dev.platform_data;
  692. pdata->max_frame_len = 1540;
  693. pdata->desc_pktlen_mask = 0xfff;
  694. err = ath79_setup_phy_if_mode(id, pdata);
  695. if (err) {
  696. printk(KERN_ERR
  697. "ar71xx: invalid PHY interface mode for GE%u\n", id);
  698. return;
  699. }
  700. if (id == 0)
  701. pdata->ddr_flush = ath79_ddr_flush_ge0;
  702. else
  703. pdata->ddr_flush = ath79_ddr_flush_ge1;
  704. switch (ath79_soc) {
  705. case ATH79_SOC_AR7130:
  706. if (id == 0)
  707. pdata->set_speed = ath79_set_speed_ge0;
  708. else
  709. pdata->set_speed = ath79_set_speed_ge1;
  710. break;
  711. case ATH79_SOC_AR7141:
  712. case ATH79_SOC_AR7161:
  713. if (id == 0)
  714. pdata->set_speed = ath79_set_speed_ge0;
  715. else
  716. pdata->set_speed = ath79_set_speed_ge1;
  717. pdata->has_gbit = 1;
  718. break;
  719. case ATH79_SOC_AR7242:
  720. if (id == 0) {
  721. pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
  722. AR71XX_RESET_GE0_PHY;
  723. pdata->set_speed = ar7242_set_speed_ge0;
  724. } else {
  725. pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
  726. AR71XX_RESET_GE1_PHY;
  727. pdata->set_speed = ath79_set_speed_dummy;
  728. }
  729. pdata->has_gbit = 1;
  730. pdata->is_ar724x = 1;
  731. if (!pdata->fifo_cfg1)
  732. pdata->fifo_cfg1 = 0x0010ffff;
  733. if (!pdata->fifo_cfg2)
  734. pdata->fifo_cfg2 = 0x015500aa;
  735. if (!pdata->fifo_cfg3)
  736. pdata->fifo_cfg3 = 0x01f00140;
  737. break;
  738. case ATH79_SOC_AR7241:
  739. if (id == 0)
  740. pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
  741. else
  742. pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
  743. /* fall through */
  744. case ATH79_SOC_AR7240:
  745. if (id == 0) {
  746. pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
  747. pdata->set_speed = ath79_set_speed_dummy;
  748. pdata->phy_mask = BIT(4);
  749. } else {
  750. pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
  751. pdata->set_speed = ath79_set_speed_dummy;
  752. pdata->speed = SPEED_1000;
  753. pdata->duplex = DUPLEX_FULL;
  754. pdata->switch_data = &ath79_switch_data;
  755. pdata->use_flow_control = 1;
  756. ath79_switch_data.phy_poll_mask |= BIT(4);
  757. }
  758. pdata->has_gbit = 1;
  759. pdata->is_ar724x = 1;
  760. if (ath79_soc == ATH79_SOC_AR7240)
  761. pdata->is_ar7240 = 1;
  762. if (!pdata->fifo_cfg1)
  763. pdata->fifo_cfg1 = 0x0010ffff;
  764. if (!pdata->fifo_cfg2)
  765. pdata->fifo_cfg2 = 0x015500aa;
  766. if (!pdata->fifo_cfg3)
  767. pdata->fifo_cfg3 = 0x01f00140;
  768. break;
  769. case ATH79_SOC_AR9132:
  770. pdata->has_gbit = 1;
  771. /* fall through */
  772. case ATH79_SOC_AR9130:
  773. if (id == 0)
  774. pdata->set_speed = ar91xx_set_speed_ge0;
  775. else
  776. pdata->set_speed = ar91xx_set_speed_ge1;
  777. pdata->is_ar91xx = 1;
  778. break;
  779. case ATH79_SOC_AR9330:
  780. case ATH79_SOC_AR9331:
  781. if (id == 0) {
  782. pdata->reset_bit = AR933X_RESET_GE0_MAC |
  783. AR933X_RESET_GE0_MDIO;
  784. pdata->set_speed = ath79_set_speed_dummy;
  785. pdata->phy_mask = BIT(4);
  786. } else {
  787. pdata->reset_bit = AR933X_RESET_GE1_MAC |
  788. AR933X_RESET_GE1_MDIO;
  789. pdata->set_speed = ath79_set_speed_dummy;
  790. pdata->speed = SPEED_1000;
  791. pdata->has_gbit = 1;
  792. pdata->duplex = DUPLEX_FULL;
  793. pdata->switch_data = &ath79_switch_data;
  794. pdata->use_flow_control = 1;
  795. ath79_switch_data.phy_poll_mask |= BIT(4);
  796. }
  797. pdata->is_ar724x = 1;
  798. if (!pdata->fifo_cfg1)
  799. pdata->fifo_cfg1 = 0x0010ffff;
  800. if (!pdata->fifo_cfg2)
  801. pdata->fifo_cfg2 = 0x015500aa;
  802. if (!pdata->fifo_cfg3)
  803. pdata->fifo_cfg3 = 0x01f00140;
  804. break;
  805. case ATH79_SOC_AR9341:
  806. case ATH79_SOC_AR9342:
  807. case ATH79_SOC_AR9344:
  808. case ATH79_SOC_QCA9533:
  809. if (id == 0) {
  810. pdata->reset_bit = AR934X_RESET_GE0_MAC |
  811. AR934X_RESET_GE0_MDIO;
  812. pdata->set_speed = ar934x_set_speed_ge0;
  813. } else {
  814. pdata->reset_bit = AR934X_RESET_GE1_MAC |
  815. AR934X_RESET_GE1_MDIO;
  816. pdata->set_speed = ath79_set_speed_dummy;
  817. pdata->switch_data = &ath79_switch_data;
  818. /* reset the built-in switch */
  819. ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
  820. ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
  821. }
  822. pdata->has_gbit = 1;
  823. pdata->is_ar724x = 1;
  824. pdata->max_frame_len = SZ_16K - 1;
  825. pdata->desc_pktlen_mask = SZ_16K - 1;
  826. if (!pdata->fifo_cfg1)
  827. pdata->fifo_cfg1 = 0x0010ffff;
  828. if (!pdata->fifo_cfg2)
  829. pdata->fifo_cfg2 = 0x015500aa;
  830. if (!pdata->fifo_cfg3)
  831. pdata->fifo_cfg3 = 0x01f00140;
  832. break;
  833. case ATH79_SOC_TP9343:
  834. if (id == 0) {
  835. pdata->reset_bit = AR933X_RESET_GE0_MAC |
  836. AR933X_RESET_GE0_MDIO;
  837. pdata->set_speed = ath79_set_speed_dummy;
  838. if (!pdata->phy_mask)
  839. pdata->phy_mask = BIT(4);
  840. } else {
  841. pdata->reset_bit = AR933X_RESET_GE1_MAC |
  842. AR933X_RESET_GE1_MDIO;
  843. pdata->set_speed = ath79_set_speed_dummy;
  844. pdata->speed = SPEED_1000;
  845. pdata->duplex = DUPLEX_FULL;
  846. pdata->switch_data = &ath79_switch_data;
  847. pdata->use_flow_control = 1;
  848. ath79_switch_data.phy_poll_mask |= BIT(4);
  849. }
  850. pdata->has_gbit = 1;
  851. pdata->is_ar724x = 1;
  852. if (!pdata->fifo_cfg1)
  853. pdata->fifo_cfg1 = 0x0010ffff;
  854. if (!pdata->fifo_cfg2)
  855. pdata->fifo_cfg2 = 0x015500aa;
  856. if (!pdata->fifo_cfg3)
  857. pdata->fifo_cfg3 = 0x01f00140;
  858. break;
  859. case ATH79_SOC_QCA9556:
  860. case ATH79_SOC_QCA9558:
  861. if (id == 0) {
  862. pdata->reset_bit = QCA955X_RESET_GE0_MAC |
  863. QCA955X_RESET_GE0_MDIO;
  864. pdata->set_speed = qca955x_set_speed_xmii;
  865. } else {
  866. pdata->reset_bit = QCA955X_RESET_GE1_MAC |
  867. QCA955X_RESET_GE1_MDIO;
  868. pdata->set_speed = qca955x_set_speed_sgmii;
  869. }
  870. pdata->has_gbit = 1;
  871. pdata->is_ar724x = 1;
  872. /*
  873. * Limit the maximum frame length to 4095 bytes.
  874. * Although the documentation says that the hardware
  875. * limit is 16383 bytes but that does not work in
  876. * practice. It seems that the hardware only updates
  877. * the lowest 12 bits of the packet length field
  878. * in the RX descriptor.
  879. */
  880. pdata->max_frame_len = SZ_4K - 1;
  881. pdata->desc_pktlen_mask = SZ_16K - 1;
  882. if (!pdata->fifo_cfg1)
  883. pdata->fifo_cfg1 = 0x0010ffff;
  884. if (!pdata->fifo_cfg2)
  885. pdata->fifo_cfg2 = 0x015500aa;
  886. if (!pdata->fifo_cfg3)
  887. pdata->fifo_cfg3 = 0x01f00140;
  888. break;
  889. case ATH79_SOC_QCA956X:
  890. if (id == 0) {
  891. pdata->reset_bit = QCA955X_RESET_GE0_MAC |
  892. QCA955X_RESET_GE0_MDIO;
  893. if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
  894. pdata->set_speed = qca956x_set_speed_sgmii;
  895. else
  896. pdata->set_speed = ar934x_set_speed_ge0;
  897. } else {
  898. pdata->reset_bit = QCA955X_RESET_GE1_MAC |
  899. QCA955X_RESET_GE1_MDIO;
  900. pdata->set_speed = ath79_set_speed_dummy;
  901. pdata->switch_data = &ath79_switch_data;
  902. pdata->speed = SPEED_1000;
  903. pdata->duplex = DUPLEX_FULL;
  904. pdata->use_flow_control = 1;
  905. /* reset the built-in switch */
  906. ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
  907. ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
  908. }
  909. pdata->has_gbit = 1;
  910. pdata->is_ar724x = 1;
  911. if (!pdata->fifo_cfg1)
  912. pdata->fifo_cfg1 = 0x0010ffff;
  913. if (!pdata->fifo_cfg2)
  914. pdata->fifo_cfg2 = 0x015500aa;
  915. if (!pdata->fifo_cfg3)
  916. pdata->fifo_cfg3 = 0x01f00140;
  917. break;
  918. default:
  919. BUG();
  920. }
  921. switch (pdata->phy_if_mode) {
  922. case PHY_INTERFACE_MODE_GMII:
  923. case PHY_INTERFACE_MODE_RGMII:
  924. case PHY_INTERFACE_MODE_SGMII:
  925. if (!pdata->has_gbit) {
  926. printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
  927. id);
  928. return;
  929. }
  930. /* fallthrough */
  931. default:
  932. break;
  933. }
  934. if (!is_valid_ether_addr(pdata->mac_addr)) {
  935. random_ether_addr(pdata->mac_addr);
  936. printk(KERN_DEBUG
  937. "ar71xx: using random MAC address for eth%d\n",
  938. ath79_eth_instance);
  939. }
  940. if (pdata->mii_bus_dev == NULL) {
  941. switch (ath79_soc) {
  942. case ATH79_SOC_AR9341:
  943. case ATH79_SOC_AR9342:
  944. case ATH79_SOC_AR9344:
  945. if (id == 0)
  946. pdata->mii_bus_dev = &ath79_mdio0_device.dev;
  947. else
  948. pdata->mii_bus_dev = &ath79_mdio1_device.dev;
  949. break;
  950. case ATH79_SOC_AR7241:
  951. case ATH79_SOC_AR9330:
  952. case ATH79_SOC_AR9331:
  953. case ATH79_SOC_QCA9533:
  954. case ATH79_SOC_TP9343:
  955. pdata->mii_bus_dev = &ath79_mdio1_device.dev;
  956. break;
  957. case ATH79_SOC_QCA9556:
  958. case ATH79_SOC_QCA9558:
  959. /* don't assign any MDIO device by default */
  960. break;
  961. case ATH79_SOC_QCA956X:
  962. if (pdata->phy_if_mode != PHY_INTERFACE_MODE_SGMII)
  963. pdata->mii_bus_dev = &ath79_mdio1_device.dev;
  964. break;
  965. default:
  966. pdata->mii_bus_dev = &ath79_mdio0_device.dev;
  967. break;
  968. }
  969. }
  970. /* Reset the device */
  971. ath79_device_reset_set(pdata->reset_bit);
  972. msleep(100);
  973. ath79_device_reset_clear(pdata->reset_bit);
  974. msleep(100);
  975. platform_device_register(pdev);
  976. ath79_eth_instance++;
  977. }
  978. void __init ath79_set_mac_base(unsigned char *mac)
  979. {
  980. memcpy(ath79_mac_base, mac, ETH_ALEN);
  981. }
  982. void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
  983. {
  984. int t;
  985. t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
  986. &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
  987. if (t != ETH_ALEN)
  988. t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
  989. &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
  990. if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
  991. memset(mac, 0, ETH_ALEN);
  992. printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
  993. mac_str);
  994. }
  995. }
  996. static void __init ath79_set_mac_base_ascii(char *str)
  997. {
  998. u8 mac[ETH_ALEN];
  999. ath79_parse_ascii_mac(str, mac);
  1000. ath79_set_mac_base(mac);
  1001. }
  1002. static int __init ath79_ethaddr_setup(char *str)
  1003. {
  1004. ath79_set_mac_base_ascii(str);
  1005. return 1;
  1006. }
  1007. __setup("ethaddr=", ath79_ethaddr_setup);
  1008. static int __init ath79_kmac_setup(char *str)
  1009. {
  1010. ath79_set_mac_base_ascii(str);
  1011. return 1;
  1012. }
  1013. __setup("kmac=", ath79_kmac_setup);
  1014. void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
  1015. int offset)
  1016. {
  1017. int t;
  1018. if (!dst)
  1019. return;
  1020. if (!src || !is_valid_ether_addr(src)) {
  1021. memset(dst, '\0', ETH_ALEN);
  1022. return;
  1023. }
  1024. t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
  1025. t += offset;
  1026. dst[0] = src[0];
  1027. dst[1] = src[1];
  1028. dst[2] = src[2];
  1029. dst[3] = (t >> 16) & 0xff;
  1030. dst[4] = (t >> 8) & 0xff;
  1031. dst[5] = t & 0xff;
  1032. }
  1033. void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
  1034. {
  1035. int i;
  1036. if (!dst)
  1037. return;
  1038. if (!src || !is_valid_ether_addr(src)) {
  1039. memset(dst, '\0', ETH_ALEN);
  1040. return;
  1041. }
  1042. for (i = 0; i < ETH_ALEN; i++)
  1043. dst[i] = src[i];
  1044. dst[0] |= 0x02;
  1045. }